Tft substrate and manufacturing method thereof

Abstract

A TFT substrate includes, stacked in sequence from bottom to top, a backing plate, a gate electrode, a gate insulation layer, an active layer and a source electrode and a drain electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode. The source electrode and the drain electrode are respectively located at two sides of the active layer. The active layer includes two lightly-ion-doped semiconductor layers respectively connected with the source and drain electrodes and a channel-zone semiconductor layer located therebetween. The first passivation layer and the planarization layer include a first via formed therein and corresponding to the drain electrode. The second passivation layer has a second via extending through a portion of the second passivation layer inside the first via. The pixel electrode is connected through the second via to the drain electrode.

What is claimed is: 
     
         1 . A thin-film transistor (TFT) substrate, comprising, stacked in sequence from bottom to top, a backing plate, a gate electrode, a gate insulation layer, an active layer and a source electrode and a drain electrode, a first passivation layer, a planarization layer, a common electrode, a second passivation layer, and a pixel electrode;
 wherein the source electrode and the drain electrode are respectively located at two opposite sides of the active layer and in connection therewith, the source electrode and the drain electrode being both formed by subjecting a semiconductor to heavy ion doping, the active layer comprising two lightly-ion-doped semiconductor layers respectively located at two ends thereof and connected with the source electrode and the drain electrode and a channel-zone semiconductor layer located between the two lightly-ion-doped semiconductor layers; and   the first passivation layer and the planarization layer comprise a first via formed therein to correspond to and be located above the drain electrode, the second passivation layer having a portion located inside the first via and comprising a second via formed therein to extend through the portion of the second passivation layer that is located inside the first via, the pixel electrode being connected through the second via to the drain electrode.   
     
     
         2 . The TFT substrate as claimed in  claim 1 , wherein the source electrode, the drain electrode, the lightly-ion-doped semiconductor layers, and the channel-zone semiconductor layer are formed of a poly-silicon layer. 
     
     
         3 . The TFT substrate as claimed in  claim 1 , wherein the source electrode, the drain electrode, and the lightly-ion-doped semiconductor layers are doped with ions that are N-type ions, and the N-type ions are phosphorous ions. 
     
     
         4 . The TFT substrate as claimed in  claim 1 , wherein doping ion concentrations in the source electrode and the drain electrode are 1×10 14 -8×10 15  ions/cm 3 , and doping ion concentration in the lightly-ion-doped semiconductor layers is 5×10 12 -9×10 13  ions/cm 3 . 
     
     
         5 . The TFT substrate as claimed in  claim 1 , wherein the backing plate comprises a glass plate; the gate electrode is formed of a material comprising at least one of molybdenum, aluminum, copper, titanium, tungsten, and alloys thereof; the first passivation layer and the second passivation layer are each a silicon nitride layer or a stacked composite layer of a silicon nitride layer and a silicon oxide layer; the planarization layer is formed of a material comprising a transparent organic insulation material; and the common electrode and the pixel electrode are formed of materials comprising indium tin oxide.