Semiconductor structure and static random access memory

Abstract

A semiconductor structure and a static random access memory are provided. The semiconductor structure includes a base substrate, including a substrate and discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region. The semiconductor structure also includes a gate structure, across a length portion of each fin; pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region; a first pull-down doped region, in the fin on one side of the gate structure in the pull-down transistor region, wherein the first pull-down doped region is connected to an adjacent pull-up doped epitaxial layer; and a second pull-down doped region, in the fin on the another side of the gate structure in the pull-down transistor region, wherein the second pull-down doped region is a non-epitaxial layer doped region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pull-up transistor region and a pull-down transistor region adjacent to the pull-up transistor region;   a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin;   pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region;   a first pull-down doped region, in the fin on one side of the gate structure in the pull-down transistor region, wherein the first pull-down doped region is connected to an adjacent pull-up doped epitaxial layer; and   a second pull-down doped region, in the fin on the another side of the gate structure in the pull-down transistor region, wherein the second pull-down doped region is a non-epitaxial layer doped region.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein:
 the pull-up transistor region includes a PMOS region;   the pull-down transistor region includes an NMOS region;   the pull-up doped epitaxial layers include P-type ions; and   the first pull-down doped region and the second pull-down doped region include N-type ions.   
     
     
         3 . The semiconductor structure according to  claim 1 , wherein:
 the pull-up doped epitaxial layers are made of SiGe; and   a concentration of the Ge ions in the pull-up doped epitaxial layers is in a range of approximately 5.02×10 21  atoms/cm 3 -2.5×10 22  atoms/cm 3 .   
     
     
         4 . The semiconductor structure according to  claim 1 , wherein:
 the first pull-down doped region is made of SiP; and   a concentration of the P ions in the first pull-down doped region is in a range of approximately 1×10 20  atoms/cm 3 -2×10 21  atoms/cm 3 .   
     
     
         5 . The semiconductor structure according to  claim 1 , wherein:
 doped ions in the second pull-down doped region include P ions or As ions.   
     
     
         6 . The semiconductor structure according to  claim 5 , wherein:
 a concentration of the P ions in the second pull-down doped region is in a range of approximately 1×10 19  atoms/cm 3 -1×10 21  atoms/cm 3 .   
     
     
         7 . The semiconductor structure according to  claim 5 , wherein:
 a concentration of the As ions in the second pull-down doped region is in a range of approximately 1×10 21  atoms/cm 3 -1×10 22  atoms/cm 3 .   
     
     
         8 . The semiconductor structure according to  claim 1 , wherein:
 the pull-down transistor region includes a first pull-down transistor region and a second pull-down transistor region adjacent to each other, and the first pull-down transistor region is adjacent to the pull-up transistor region; and   the gate structure in the first pull-down transistor region is across a length portion of the fin in the first pull-down transistor region, and the gate structure in the second pull-down transistor region is across a length portion of the fin in the second pull-down transistor region.   
     
     
         9 . The semiconductor structure according to  claim 8 , wherein:
 the first pull-down doped region is formed in the fin on one side of the gate structure in the first pull-down transistor region;   the second pull-down doped region is formed in the fin on the other side of the gate structure in the first pull-down transistor region; and   third pull-down doped regions in the fin on both sides of the gate structure in the second pull-down transistor region are also formed when performing the in-situ doped selective epitaxial process, wherein the third pull-down doped regions are made of the same material as the first pull-down doped region.   
     
     
         10 . The semiconductor structure according to  claim 1 , wherein:
 the base substrate includes a pull-down threshold adjustment implantation, corresponding to the second pull-down doped region.   
     
     
         11 . A static random access memory including the semiconductor structure according to  claim 1 .