Integrated gate driver

Abstract

A gate driver suitable for integration with the backplane of an AMOLED display includes first and second clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of the clock signals is active the other of the clock signals is inactive, and active portions of the first and second clock signals do not overlap. In a daisy chain of circuits for producing gate signals, each of the circuits except the last has an output coupled to the input of the next circuit in the chain. A source of a start token signal is coupled to an input of a first circuit in the daisy chain. Each of the circuits is configured to produce a gate signal one clock cycle after an active portion of one of the clock signals is received.

1 - 15 . (canceled) 
     
     
         16 . A gate driver suitable for integration with the backplane of an active matrix organic light emitting diode (AMOLED) display, said gate driver comprising
 clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;   a daisy chain of circuits integrated within said backplane for producing gate signals, each of said circuits including a capacitor and a thin film transistor, and each of said circuits except the last circuit in the daisy chain having an output coupled to an input of an adjacent circuit in the daisy chain; and   a source of a start token signal coupled to an input of a first circuit in said daisy chain;   wherein each of said circuits is configured to produce a gate signal one clock cycle after an active portion of one of said clock signals is received.   
     
     
         17 . The gate driver of  claim 16  which is configured for use with an AMOLED display comprising p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage. 
     
     
         18 . The gate driver of  claim 16  in which said gate signals are active low for selecting or addressing p-type thin film transistors. 
     
     
         19 . The gate driver of  claim 16  in which said gate signals are active high for selecting or addressing n-type thin film transistors. 
     
     
         20 . The gate driver of  claim 16  in which said circuits produce consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals. 
     
     
         21 . The gate driver of  claim 20  in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals. 
     
     
         22 . An integrated gate driver for performing emission operations of a display, the gate driver comprising:
 a source of first and second clock signals each, having alternating active and inactive portions configured such that when one is active the other is inactive and active signals do not overlap;   a source for a start token signal and an inverse start token signal for input into a first circuit block;   integrated within a backplane of the display alternating odd and even circuit blocks daisy chained together such that the output of one circuit block is connected to the input of the next circuit block and each circuit block receives as inputs both first and second clock signals, wherein each circuit block includes a capacitor and a thin film transistor and is configured to produce an active output one clock cycle after an active signal is received and an inactive output at all other times.   
     
     
         23 . The integrated gate driver of  claim 22  configured for use with a display comprising p-type transistors so that an active signal corresponds with a high voltage and an inactive signal corresponds with a low voltage. 
     
     
         24 . The integrated gate driver of  claim 22  wherein the alternating circuit blocks are configured to select a line of pixels for two clock cycles in order to allow time for the pixels to settle before being programmed. 
     
     
         25 . A method of producing gate signals from a gate driver integrated with the backplane of an active matrix organic light emitting diode (AMOLED) display, said method comprising producing first and second clock signals each having alternating active and inactive portions configured such that when one of said clock signals is active the other of said clock signals is inactive, and active portions of said first and second clock signals do not overlap;
 producing gate signals from a daisy chain of circuits integrated within said backplane, each of said circuits including a capacitor and a thin film transistor, and each of said circuits except the last circuit in the daisy chain having an output coupled to the input of an adjacent circuit in the daisy chain;   supplying a start token signal to an input of a first circuit in said daisy chain; and   producing a gate signal from each of said circuits, each gate signal being produced one clock cycle after said start token signal or an active portion of one of said clock signals is received.   
     
     
         26 . The method of  claim 25  in which the AMOLED display comprises p-type transistors so that an active signal corresponds to a low voltage and an inactive signal corresponds to a high voltage. 
     
     
         27 . The method of  claim 25  in which said gate signals are active low for selecting or addressing p-type thin film transistors. 
     
     
         28 . The method of  claim 25  in which said gate signals are active high for selecting or addressing n-type thin film transistors. 
     
     
         29 . The method of  claim 25  which produces consecutive gate signals with a predetermined time gap between each pair of consecutive gate signals. 
     
     
         30 . The method of  claim 29  in which said active portions of said first and second clock signals have a predetermined time gap between them, to produce said time gap between each pair of consecutive gate signals.