US2019175004A1PendingUtilityA1

Imaging module for endoscope, and endoscope

Assignee: OLYMPUS CORPPriority: Nov 21, 2016Filed: Feb 20, 2019Published: Jun 13, 2019
Est. expiryNov 21, 2036(~10.3 yrs left)· nominal 20-yr term from priority
H10W 90/722H10W 72/267H10W 72/263H10W 72/248H10W 72/227H10W 70/656H10W 70/655H10W 70/654H10W 20/023H10W 74/127H10W 70/635H10W 70/611H10W 42/121H10W 20/20H04N 23/555H04N 25/70H04N 23/52A61B 1/00124G02B 23/2484A61B 1/051A61B 1/00114A61B 1/045H01L 2924/3512H01L 23/3142H01L 2224/16145H01L 24/17H01L 23/562H01L 2224/17517H01L 27/14618H01L 24/16H01L 27/14634H01L 27/14636A61B 1/00009H10F 39/811H10F 39/809H10F 39/804H10F 39/018
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Claims

Abstract

The disclosed technology is directed to an imaging module of an endoscope comprises a plurality of semiconductor devices includes first and second semiconductor devices being electrically stacked to one another with a sealing layer interposed therebetween to transmit signals via a signal cable connected to a rear wall of the plurality of semiconductor devices. The first semiconductor device includes respective opposed first and second major surfaces having a first central region. The first major surface includes a semiconductor circuit portion disposed in the central region thereof. A through-silicon via is disposed in an intermediate region surrounding the first central region and is connected to the semiconductor circuit portion. The second major surface includes a first electrode located in the first central region thereof. The first electrode is connected to the through-silicon via. The second semiconductor device includes respective opposed third and fourth major surfaces having a second central region.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An imaging module of an endoscope comprising:
 a plurality of semiconductor devices includes respective first and second semiconductor devices being electrically stacked to one another with a sealing layer interposed therebetween to transmit signals via a signal cable connected to a rear wall of a rearmost one of the plurality of semiconductor devices;   the first semiconductor device includes respective opposed first and second major surfaces having a first central region, the first major surface includes a semiconductor circuit portion disposed in the central region thereof, a through-silicon via disposed in an intermediate region surrounding the first central region wherein the through-silicon via being connected to the semiconductor circuit portion, the second major surface includes a first electrode located in the first central region thereof wherein the first electrode being connected to the through-silicon via;   the second semiconductor device includes respective opposed third and fourth major surfaces having a second central region, the third major surface includes a second electrode disposed in the second central region thereof;   the rearmost semiconductor device includes an external connection terminal disposed on the rear wall thereof and to which the signal cable is connected; and   at least one bonding portion being disposed between the first electrode and the second electrode in the respective first and second central regions.   
     
     
         2 . The imaging module of  claim 1 , wherein the at least one bonding portion is defined by a plurality of bonding portions arranged in a circular pattern. 
     
     
         3 . The imaging module of  claim 2 , wherein the plurality of bonding portions is arranged in a concentric circular pattern. 
     
     
         4 . The imaging module of  claim 2 , wherein among the plurality of bonding portions, those which are arranged on a side of an inner circumference are smaller in size than those which are arranged on a side of an outer circumference. 
     
     
         5 . The imaging module of  claim 1  further comprising:
 a dummy bonding portion disposed in the respective first and second central regions on a side of a circumference outer than a region in which each bonding portion is disposed without electrically connecting the first semiconductor device and the second semiconductor device to one another. 
 
     
     
         6 . The imaging module of  claim 1 , wherein the sealing layer includes a first sealing layer disposed in the respective first and second central regions, and a second sealing layer disposed in an outer peripheral region, which surrounds the intermediate region, and having a smaller Young's modulus than the first sealing layer. 
     
     
         7 . The imaging module of  claim 6 , wherein the first sealing layer is disposed in the intermediate region. 
     
     
         8 . The imaging module of  claim 1 , wherein the first semiconductor device is the imaging device that includes a light-receiving portion as the semiconductor circuit portion. 
     
     
         9 . The imaging module of  claim 1 , wherein the plurality of semiconductor devices has a third semiconductor device similar to the first semiconductor device or the second semiconductor device wherein the first, second and third semiconductor device are stacked to one another with a sealing layer having the same configuration as the sealing layer and interposed between each two adjacent semiconductor devices. 
     
     
         10 . The imaging module of  claim 1  used in the endoscope further includes:
 the signal cable connected to the external connection terminal; 
 an insertion portion with the imaging module accommodated in a tip portion thereof; 
 a control portion disposed on a side of a proximal end of the insertion portion; and 
 a universal cord extending from the control portion, wherein 
 the universal cord is electrically connected to the signal cable while the signal cable is connected to the external connection terminal. 
 
     
     
         11 . An imaging module comprising:
 a first semiconductor; and   a second semiconductor configured to be electrically attached to the first semiconductor through a sealing layer, wherein
 the first semiconductor having opposed first and second surfaces, the first surface having a first central region and a first intermediate region surrounding the first central region, the second surface having a second central region, the first semiconductor including:
 a semiconductor circuit in the first central region; 
 a through-silicon via in the first intermediate region, the through-silicon via being connected to the semiconductor circuit; and 
 a first electrode in the second central region, the first electrode being connected to the through-silicon via; 
 
   the second semiconductor having opposed third and fourth surfaces, the third surface having a third central region, the second semiconductor including a second electrode in the third central region,   and   a bump disposed between the first electrode in the second central region and the second electrode in the third central region.   
     
     
         12 . The imaging module of  claim 11 , wherein the first semiconductor includes an imaging device. 
     
     
         13 . The imaging module of  claim 11 , wherein the imaging module includes a plurality of semiconductors, the plurality of semiconductors includes the first semiconductor and the second semiconductor, a rearmost semiconductor of the plurality of semiconductor includes a rear wall. 
     
     
         14 . The imaging module of  claim 13 , wherein the imaging module transmits signals via a signal cable connected to the real wall. 
     
     
         15 . The imaging module of  claim 13 , wherein the rearmost semiconductor has an external connection terminal disposed on the rear wall, the signal cable being connected to the external connection. 
     
     
         16 . The imaging module of  claim 11 , wherein
 the bump includes a first plurality of bumps and a second plurality of bumps arranged in a concentric circular pattern, the first plurality of bumps forming an inner circle and the second plurality of bumps forming an outer circle, the first plurality of bumps are smaller in size than the second plurality of bumps.   
     
     
         17 . The imaging module of  claim 11 , further comprising:
 a dummy electrode disposed in an outer region of the second central region, the outer region is outer than a region that the first electrode is disposed, the dummy bump not being electrically connecting between the first semiconductor and the second semiconductor.   
     
     
         18 . The imaging module of  claim 11 , wherein the sealing layer includes a first sealing layer and a second sealing layer surrounding the first sealing layer, the second sealing layer having a smaller Young's modulus than the first sealing layer. 
     
     
         19 . The imaging module of  claim 18 , wherein the first sealing layer facing the second central region and the third central region. 
     
     
         20 . The imaging module of  claim 19 , wherein the first sealing layer facing a second intermediate region surrounding the second central region and a third intermediate region surrounding the third central region.

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