Reference disturbance mitigation in successive approximation register analog to digital converter

Abstract

The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

1 - 20 . (canceled) 
     
     
         21 . A successive approximation register analog to digital converter for use at an analog output, the successive approximation register analog to digital converter comprising:
 a comparator;   a capacitor array coupled to an input of the comparator; and   a switch array configured to be activated to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection.   
     
     
         22 . The successive approximation register of  claim 21  wherein to couple a previous bit capacitor of the capacitor array to a fine reference connection includes to simultaneously couple a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. 
     
     
         23 . The successive approximation register of  claim 22  wherein the group of previous bit capacitors includes a most significant bit capacitor. 
     
     
         24 . The successive approximation register of  claim 22  wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. 
     
     
         25 . The successive approximation register of  claim 21  wherein activation of the switch array does not couple a least significant bit capacitor of the capacitor array to the fine reference. 
     
     
         26 . The successive approximation register of  claim 21  wherein activation of the switch array does not couple a number of smallest capacitors of the capacitor array to the fine reference. 
     
     
         27 . A semiconductor die assembly comprising:
 a comparator mounted on a semiconductor die;   a capacitor array, the capacitor array mounted on the semiconductor die;   a switch array mounted on the semiconductor die; and   a successive approximation register sequencer configured to activate the switch array to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection, the successive approximation register sequencer mounted on the semiconductor die.   
     
     
         28 . The die assembly of  claim 27  wherein coupling the previous bit capacitor to the fine reference connection includes coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. 
     
     
         29 . The die assembly of  claim 28  wherein the group of previous bit capacitors includes a most significant bit capacitor. 
     
     
         30 . The die assembly of  claim 28  wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. 
     
     
         31 . The die assembly of  claim 27  wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a least significant bit capacitor to the fine reference. 
     
     
         32 . The die assembly of  claim 27  wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a specified number of smallest capacitors to the fine reference. 
     
     
         33 . The die assembly of  claim 27  wherein the fine reference connection includes a fine positive reference connection, a fine negative reference connection, or combinations thereof. 
     
     
         34 . The die assembly of  claim 27  wherein the rough reference connection includes a rough positive reference connection, a rough negative reference connection, or combinations thereof. 
     
     
         35 . An analog to digital converter circuit assembly comprising:
 a comparator;   a capacitor array;   a switch array configured to selectively couple the capacitor array to an analog signal input and to reference connections; and   a successive approximation register sequencer configured to activate the switch array to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection.   
     
     
         36 . The circuit assembly of  claim 35  wherein the successive approximation register sequencer is further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection and simultaneously coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. 
     
     
         37 . The circuit assembly of  claim 36  wherein the group of previous bit capacitors includes a most significant bit capacitor. 
     
     
         38 . The circuit assembly of  claim 36  wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. 
     
     
         39 . The circuit assembly of  claim 35  wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a least significant bit capacitor to the fine reference. 
     
     
         40 . The circuit assembly of  claim 35  wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a specified number of smallest capacitors to the fine reference.