Semiconductor Device with Integrated pn Diode Temperature Sensor

Abstract

A semiconductor device includes a semiconductor substrate having a first region with one or more transistor cells and a second region devoid of transistor cells, a first dielectric material over the first region and the second region of the semiconductor substrate, a second dielectric material over the first dielectric material, a pn diode formed in the first dielectric material over the second region of the semiconductor substrate, a plurality of first contacts extending from above the pn diode and into a p-type region of the pn diode so that the p-type region abuts sidewalls of each first contact, and a plurality of second contacts extending from above the pn diode and into an n-type region of the pn diode so that the n-type region abuts sidewalls of each second contact.

1 . A semiconductor device, comprising:
 a semiconductor substrate having a first region with one or more transistor cells and a second region devoid of transistor cells;   a first dielectric material over the first region and the second region of the semiconductor substrate;   a second dielectric material over the first dielectric material;   a pn diode formed in the first dielectric material over the second region of the semiconductor substrate;   a plurality of first contacts electrically connected to an anode electrode of the pn diode and extending from above the pn diode and into a p-type region of the pn diode so that the p-type region abuts sidewalls of each first contact; and   a plurality of second contacts electrically connected to a cathode electrode of the pn diode and extending from above the pn diode and into an n-type region of the pn diode so that the n-type region abuts sidewalls of each second contact.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the plurality of first contacts extends through the p-type region of the pn diode and into a lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein the plurality of second contacts extends through the n-type region of the pn diode and into the lower layer of the first dielectric material. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the plurality of first contacts terminates within the p-type region of the pn diode before reaching a lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein the plurality of second contacts terminates within the n-type region of the pn diode before reaching the lower layer of the first dielectric material. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first dielectric material comprises a first layer and a second layer over the first layer, and wherein the pn diode is formed between the first layer and the second layer over the second region of the semiconductor substrate. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first layer of the first dielectric material is thicker than the second layer of the first dielectric material. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the plurality of first contacts comprises rows of the first contacts that extend generally parallel with one another, and wherein the plurality of second contacts comprises rows of the second contacts that extend generally parallel with one another. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the plurality of first contacts is arranged in a first checkerboard pattern, and wherein the plurality of second contacts is arranged in a second checkerboard pattern. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a third dielectric material over the second region of the semiconductor substrate but not the first region, wherein the first dielectric material is separated from the semiconductor substrate by the third dielectric material. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the pn diode comprises polycrystalline or amorphous silicon having a thickness between 300 nm and 950 nm. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the first dielectric material comprises undoped silicate glass (USG), wherein the second dielectric material comprises borophosphosilicate glass (BPSG), and wherein the pn diode comprises polycrystalline or amorphous silicon. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the first dielectric material and the second dielectric material are etched back around the perimeter of each first contact and each second contact so that the pn diode is not covered by the first dielectric material or the second dielectric material in each region wherein the first dielectric material and the second dielectric material are etched back. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the plurality of first contacts is spaced at least 50 μm from a first edge of the pn diode along which the plurality of first contacts runs parallel, and wherein the plurality of second contacts is spaced at least 50 μm from a second edge of the pn diode along which the plurality of second contacts runs parallel. 
     
     
         13 . A method of manufacturing a semiconductor device, the method comprising:
 forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells;   forming a first dielectric material over the first region and the second region of the semiconductor substrate;   forming a second dielectric material over the first dielectric material;   forming a pn diode in the first dielectric material over the second region of the semiconductor substrate;   forming a plurality of first contacts that extend from above the pn diode and into a p-type region of the pn diode so that the p-type region abuts sidewalls of each first contact; and   forming a plurality of second contacts that extend from above the pn diode and into an n-type region of the pn diode so that the n-type region abuts sidewalls of each second contact.   
     
     
         14 . The method of  claim 13 , wherein forming the plurality of first contacts and forming the plurality of second contacts comprises:
 etching first contact grooves through the p-type region of the pn diode and into a lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate;   etching second contact grooves through the n-type region of the pn diode and into the lower layer of the first dielectric material; and   filling the first contact grooves and the second contact grooves with an electrically conductive material.   
     
     
         15 . The method of  claim 13 , wherein forming the plurality of first contacts and forming the plurality of second contacts comprises:
 etching first contact grooves which terminate within the p-type region of the pn diode before reaching a lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate;   etching second contact grooves which terminate within the n-type region of the pn diode before reaching the lower layer of the first dielectric material; and   filling the first contact grooves and the second contact grooves with an electrically conductive material.   
     
     
         16 . The method of  claim 13 , wherein the plurality of first contacts and the plurality of second contacts are formed as part of a common contact formation process, wherein during the common contact formation process a plurality of third contacts which extend into the first region of the semiconductor substrate are formed at the same time as the plurality of first contacts and the plurality of second contacts, and wherein the common contact formation process is photolithographically focused on the first region of the semiconductor substrate and not focused on the pn diode. 
     
     
         17 . The method of  claim 16 , wherein the common contact formation process comprises:
 forming a plurality of first contact grooves, a plurality of second contact grooves and a plurality of third contact grooves at the same time, the plurality of first contact grooves extending through the second dielectric material, through an upper layer of the first dielectric material covering the pn diode and into the p-type region of the pn diode, the plurality of second contact grooves extending through the second dielectric material, through the upper layer of the first dielectric material and into the n-type region of the pn diode, and the plurality of third contact grooves extending through the second dielectric material, through the first dielectric material and into the first region of the semiconductor substrate; and   filling the plurality of first contact grooves, the plurality of second contact grooves and the plurality of third contact grooves with an electrically conductive material.   
     
     
         18 . The method of  claim 17 , further comprising:
 prior to filling the contact grooves with the electrically conductive material, implanting p-type dopants into the plurality of first contact grooves, the plurality of second contact grooves and the plurality of third contact grooves.   
     
     
         19 . The method of  claim 18 , further comprising:
 after implanting the p-type dopants and prior to filling the contact grooves with the electrically conductive material, etching back the first dielectric material and the second dielectric material around the perimeter of each first contact groove and each second contact groove so that the pn diode is not covered by the first dielectric material or the second dielectric material in each region wherein the first dielectric material and the second dielectric material are etched back.   
     
     
         20 . The method of  claim 17 , wherein the plurality of first contact grooves extends through the p-type region of the pn diode and into a lower layer of the first dielectric material disposed between the pn diode and the semiconductor substrate, and wherein the plurality of second contact grooves extends through the n-type region of the pn diode and into the lower layer of the first dielectric material. 
     
     
         21 . The method of  claim 17 , further comprising:
 spacing the plurality of first contact grooves at least 50 μm from a first edge of the pn diode along which the plurality of first contact grooves runs parallel; and   spacing the plurality of second contact grooves at least 50 μm from a second edge of the pn diode along which the plurality of second contact grooves runs parallel.   
     
     
         22 . The method of  claim 13 , wherein forming the first dielectric material and forming the pn diode comprises:
 forming a first layer of the first dielectric material over the first region and the second region of the semiconductor substrate;   forming polycrystalline or amorphous silicon on the first layer of the first dielectric material over the second region but not the first region of the semiconductor substrate; and   forming a second layer of the first dielectric material on the first layer over the first region of the semiconductor substrate and on the polycrystalline or amorphous silicon over the second region of the semiconductor substrate.