High Density Split-Gate Memory Cell

Abstract

A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

What is claimed is: 
     
         1 . A memory device, comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, 
 a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first coupling gate disposed over and insulated from the first floating gate, and 
 a second coupling gate disposed over and insulated from the second floating gate; 
   control circuitry configured to read one of the pairs of memory cells by applying to the one pair of memory cells:
 a zero voltage to the first region, 
 a positive voltage to the second region, 
 a zero or positive voltage to the first coupling gate, 
 a positive voltage to the second coupling gate, and 
 a positive voltage to the erase gate; 
   and by detecting an electrical current through the channel region.   
     
     
         2 . A memory device, comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, 
 a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first coupling gate disposed over and insulated from the first floating gate, and 
 a second coupling gate disposed over and insulated from the second floating gate; 
   control circuitry configured to program one of the pairs of memory cells by applying to the one pair of memory cells:
 a first positive voltage to the first region, 
 a current to the second region, 
 a second positive voltage to the first coupling gate, 
 a third positive voltage to the second coupling gate, and 
 a fourth positive voltage to the erase gate. 
   
     
     
         3 . The memory device of  claim 2 , wherein the second positive voltage is greater than the first, second and third positive voltages. 
     
     
         4 . The memory device of  claim 2 , wherein the first positive voltage is greater than the third and fourth positive voltages. 
     
     
         5 . A memory device, comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, 
 a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first coupling gate disposed over and insulated from the first floating gate, and 
 a second coupling gate disposed over and insulated from the second floating gate; 
   control circuitry configured to erase one of the pairs of memory cells by applying to the one pair of memory cells:
 a zero voltage to the first region, 
 a zero voltage to the second region, 
 a first negative voltage to the first coupling gate, 
 a second negative voltage to the second coupling gate, and 
 a positive voltage to the erase gate. 
   
     
     
         6 . The memory device of  claim 5 , wherein the first and second negative voltages are the same. 
     
     
         7 . A memory device, comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, 
 a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first coupling gate disposed over and insulated from the first floating gate, and 
 a second coupling gate disposed over and insulated from the second floating gate; 
   control circuitry configured to erase one memory cell of a pair of memory cells by applying to the one pair of memory cells:
 a zero voltage to the first region, 
 a zero voltage to the second region, 
 a first negative voltage to the first coupling gate, 
 a zero or positive voltage to the second coupling gate, and 
 a positive voltage to the erase gate.