Electrostatic discharge protection circuit with a high turn-on speed

Abstract

An electrostatic discharge (ESD) protection circuit includes an ESD release transistor, at least one stress release transistor, a control circuit, and a voltage division circuit. The ESD release transistor is coupled to a reference voltage terminal of a circuit to be protected. The at least one stress release transistor is coupled between a voltage input terminal of the circuit to be protected and the ESD release transistor. The control circuit turns off the ESD release transistor during a normal operation, and turns on the ESD release transistor during a positive ESD zapping. The voltage division circuit provides at least one divisional voltage for turning on the at least one stress release transistor during the normal operation and the positive ESD zapping.

What is claimed is: 
     
         1 . An electrostatic discharge (ESD) protection circuit comprising:
 an ESD release transistor coupled to a reference voltage terminal configured to provide a reference voltage for a circuit to be protected;   at least one stress release transistor coupled between a voltage input terminal configured to provide an input voltage for the circuit to be protected and the ESD release transistor;   a control circuit configured to turn off the ESD release transistor during a normal operation, and turn on the ESD release transistor during a positive ESD zapping; and   a voltage division circuit configured to provide at least one divisional voltage according to the input voltage provided from the voltage input terminal for turning on the at least one stress release transistor during the normal operation and the positive ESD zapping.   
     
     
         2 . The electrostatic discharge protection circuit of  claim 1 ,
 wherein the voltage division circuit comprises:   a first reference voltage node coupled to a control terminal of a first stress release transistor of the at least one stress release transistor, and configured to provide a first divisional voltage; and   a first set of diodes coupled in series between the voltage input terminal and the first reference voltage node.   
     
     
         3 . The electrostatic discharge protection circuit of  claim 2 ,
 wherein the voltage division circuit further comprises:   a first capacitor coupled in parallel with the first set of diodes.   
     
     
         4 . The electrostatic discharge protection circuit of  claim 2 ,
 wherein the control circuit comprises:   a second capacitor having a first terminal coupled to the first reference voltage node, and a second terminal coupled to a control terminal of the ESD release transistor.   
     
     
         5 . The electrostatic discharge protection circuit of  claim 4 ,
 wherein the second capacitor is implemented by a metal-oxide-semiconductor transistor.   
     
     
         6 . The electrostatic discharge protection circuit of  claim 4 ,
 wherein the control circuit further comprises:   a transient resistor coupled between the second terminal of the second capacitor and the reference voltage terminal.   
     
     
         7 . The electrostatic discharge protection circuit of  claim 2 ,
 wherein the voltage division circuit further comprises:   a second reference voltage node coupled to a control terminal of a second stress release transistor of the at least one stress release transistor, and configured to provide a second divisional voltage; and   a second set of diodes coupled in series between the first reference voltage node and the second reference voltage node.   
     
     
         8 . The electrostatic discharge protection circuit of  claim 1 ,
 wherein the voltage division circuit comprises:   a first reference voltage node coupled to a control terminal of a first stress release transistor of the at least one stress release transistor, and configured to provide a first divisional voltage;   a first resistor coupled between the voltage input terminal and the first reference voltage node; and   a second resistor coupled between the first reference voltage node and the reference voltage terminal.   
     
     
         9 . The electrostatic discharge protection circuit of  claim 8 ,
 wherein the control circuit comprises:   a first capacitor having a first terminal coupled to the voltage input terminal, and a second terminal; and   a second capacitor having a first terminal coupled to the second terminal of the first capacitor, and a second terminal coupled to a control terminal of the ESD release transistor.   
     
     
         10 . The electrostatic discharge protection circuit of  claim 9 ,
 wherein the control circuit further comprises:   a transient resistor coupled between the second terminal of the second capacitor and the reference voltage terminal.   
     
     
         11 . The electrostatic discharge protection circuit of  claim 8 ,
 wherein the voltage division circuit further comprises:   a second reference voltage node coupled to the second resistor and a control terminal of a second stress release transistor of the at least one stress release transistor, and configured to provide a second divisional voltage; and   a third resistor coupled between the second reference voltage node and the reference voltage terminal.   
     
     
         12 . The electrostatic discharge protection circuit of  claim 1 , wherein
 the at least one stress release transistor and the ESD release transistor are N-type transistors;   a body terminal of the at least one stress release transistor and a body terminal of the ESD release transistor are coupled to the reference voltage terminal; and   during a negative ESD zapping, an ESD release current flows from the reference voltage terminal to the voltage input terminal through the body terminal of the at least one stress release transistor and the body terminal of the ESD release transistor.