Virtual Ground Non-volatile Memory Array

Abstract

A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

What is claimed is: 
     
         1 . A memory device comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, 
 a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first control gate disposed vertically over and insulated from the first floating gate, and 
 a second control gate disposed vertically over and insulated from the second floating gate; 
   wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;   a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;   a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;   a plurality of bit lines having lengths extending in the second direction and each electrically connected to one of the first regions and one of the second regions in each of the active regions;   a plurality of erase gate lines having lengths extending in the first direction and each electrically connected to the erase gates in one of the active regions.   
     
     
         2 . The memory device of  claim 1 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the memory cells that are not the selected memory cell. 
   
     
     
         3 . The memory device of  claim 1 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; and 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell. 
   
     
     
         4 . The memory device of  claim 3 , wherein the control circuitry is configured further to apply:
 a negative voltage to the control gate lines electrically connected to the control gates of a memory cell pair adjacent to the memory cell pair containing the selected memory cell; and   a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell and not adjacent to the pair of memory cells containing the selected memory cell.   
     
     
         5 . The memory device of  claim 1 , further comprising:
 control circuitry configured to, during an erase operation for a selected one of the memory cells, apply:
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; and 
 a negative voltage to the control gate line electrically connected to the control gate of the selected memory cell. 
   
     
     
         6 . A memory device comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, 
 a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, 
 an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first control gate disposed vertically over and insulated from the first floating gate, and 
 a second control gate disposed vertically over and insulated from the second floating gate; 
   wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;   a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;   a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions; and   a plurality of erase gate lines having lengths extending in the second direction and each electrically connected to one of the erase gates in each of the active regions.   
     
     
         7 . The memory device of  claim 6 , further comprising:
 a plurality of bit lines each having a zig zag configuration that includes:
 first portions disposed vertically over and electrically connected to some of the first and second regions of a first of the active regions; 
 second portions disposed vertically over and electrically connected to some of the first and second regions of a second of the active regions adjacent to the first of the active regions; and 
 third portions each traversing the isolation region between the first and second active regions. 
   
     
     
         8 . The memory device of  claim 7 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell. 
   
     
     
         9 . The memory device of  claim 7 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell. 
   
     
     
         10 . The memory device of  claim 9 , wherein the control circuitry is further configured to apply:
 a positive voltage to the bit line electrically connected to the pair of memory cells not containing the selected memory cell and sharing the bit line and control gate line electrically connected to the selected memory cell.   
     
     
         11 . The memory device of  claim 9 , wherein the control circuitry is further configured to apply:
 a positive or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell and not sharing the bit line and control gate line electrically connected to the selected memory cell; and   a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.   
     
     
         12 . The memory device of  claim 6 , further comprising:
 a plurality of bit lines each electrically connected to one of the first regions and one of the second regions in each of the active regions, wherein each of the bit lines is diagonally oriented relative to the first direction.   
     
     
         13 . The memory device of  claim 6 , further comprising:
 a plurality of bit lines each electrically connected to one of the first regions and one of the second regions in each of the active regions, wherein each of the bit lines includes:
 first segments each having a length extending along one of the active regions, and 
 second segments each traversing across one of the isolation regions from one of the first segments to another of the first segments. 
   
     
     
         14 . The memory device of  claim 12 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell. 
   
     
     
         15 . The memory device of  claim 12 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell. 
   
     
     
         16 . The memory device of  claim 15 , wherein the control circuitry is further configured to apply:
 a positive voltage to the bit line electrically connected to the pair of memory cells not containing the selected memory cell and sharing the bit line and control gate line electrically connected to the selected memory cell; and   a positive or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell and not sharing the bit line and control gate line electrically connected to the selected memory cell;   
     
     
         17 . The memory device of  claim 15 , wherein the control circuitry is further configured to apply:
 a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.   
     
     
         18 . The memory device of  claim 6 , wherein each of the active regions further comprises:
 a first bit line having a length extending in the first direction and electrically connected to some of the first and second regions in the active region; and   a second bit line having a length extending in the first direction and electrically connected to others of the first and second regions in the active region.   
     
     
         19 . The memory device of  claim 18 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a positive voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell. 
   
     
     
         20 . The memory device of  claim 18 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
   
     
     
         21 . The memory device of  claim 20 , wherein the control circuitry is further configured to apply:
 a positive voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and   a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.   
     
     
         22 . The memory device of  claim 6 , wherein:
 for each one of the active regions:
 a first plurality of the first regions in the one active region are electrically connected to a first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction; 
 a second plurality of the first regions in the one active region are electrically connected to a second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction; 
 wherein the first plurality of the first regions alternate with the second plurality of the first regions; 
   the memory device further comprising:
 a first plurality of bit lines each having a length extending along one of a first plurality of the active regions and electrically connected to the first plurality of the first regions therein; and 
 a second plurality of bit lines each having a length extending along one of a second plurality of the active regions and electrically connected to the second plurality of the first regions therein; 
 wherein the first plurality of the active regions alternate with the second plurality of the active regions. 
   
     
     
         23 . The memory device of  claim 22 , wherein for each one of the active regions:
 the first plurality of the first regions in the one active region are electrically connected to the first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction by diffusion extending across one of the isolation regions; and   the second plurality of the first regions in the one active region are electrically connected to the second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction by diffusion extending across another one of the isolation regions.   
     
     
         24 . The memory device of  claim 22 , wherein for each one of the active regions:
 the first plurality of the first regions in the one active region are electrically connected to the first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction by metal connectors extending across one of the isolation regions; and   the second plurality of the first regions in the one active region are electrically connected to the second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction by metal connectors extending across another one of the isolation regions.   
     
     
         25 . The memory device of  claim 22 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a zero voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell. 
   
     
     
         26 . The memory device of  claim 22 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell. 
   
     
     
         27 . The memory device of  claim 26 , wherein the control circuitry is further configured to apply:
 a positive voltage or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and   a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.   
     
     
         28 . A memory device, comprising:
 a substrate of semiconductor material of a first conductivity type;   spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;   each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
 first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, 
 a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, 
 a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, 
 an word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, 
 a first control gate disposed over and insulated from the first floating gate, 
 a second control gate disposed over and insulated from the second floating gate, 
 a first erase gate disposed over and insulated from the first region, and 
 a second erase gate disposed over and insulated from the second region; 
   wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.   
     
     
         29 . The memory device of  claim 28 , further comprising:
 a plurality of first control gate lines extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;   a plurality of second control gate lines extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;   a plurality of erase gate lines extending in the second direction and each electrically connected to one of the first and second erase gates in each of the active regions; and   a plurality of word lines extending in the second direction and each electrically connected to one of the word line gates in each of the active regions.   
     
     
         30 . The memory device of  claim 29 , wherein:
 for each one of the active regions:
 a first plurality of the erase gates in the one active region are electrically connected to a first plurality of the erase gates in another of the active regions adjacent to the one active region in the second direction; 
 a second plurality of the erase gates in the one active region are electrically connected to a second plurality of the erase gates in another of the active regions adjacent to the one active region in a direction opposite to the second direction; 
 wherein the first plurality of the erase gates alternate with the second plurality of the erase gates. 
   
     
     
         31 . The memory device of  claim 30 , further comprising:
 a first plurality of electrical contacts each electrically connected between one of the first plurality of the erase gates and one of the erase gate lines; and   a second plurality of electrical contacts each electrically connected between one of the second plurality of the erase gates and one of the erase gate lines.   
     
     
         32 . The memory device of  claim 29 , wherein:
 for each one of the active regions:
 a first plurality of the first regions in the one active region are electrically connected to a first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction; 
 a second plurality of the first regions in the one active region are electrically connected to a second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction; 
 wherein the first plurality of the first regions alternate with the second plurality of the first regions; 
   the memory device further comprising:
 a first plurality of bit lines each extending parallel to one of a first plurality of the active regions and electrically connected to the first plurality of the first regions therein; and 
 a second plurality of bit lines each extending parallel to one of a second plurality of the active regions and electrically connected to the second plurality of the first regions therein; 
 wherein the first plurality of the active regions alternate with the second plurality of the active regions. 
   
     
     
         33 . The memory device of  claim 32 , wherein each of the first and second pluralities of bits lines extends over one of the isolation regions. 
     
     
         34 . The memory device of  claim 33 , further comprising:
 a plurality of metal bridges each extending in the first direction between a first contact that is electrically connected to one of the first and second regions, and a second contact that is electrically connected to one of the first and second plurality of bit lines.   
     
     
         35 . The memory device of  claim 32 , further comprising:
 control circuitry configured to, during a read operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 a zero voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the word line electrically connected to the word line gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and 
 a zero voltage to the word lines electrically connected to the word line gates of the pairs of memory cells not containing the selected memory cell. 
   
     
     
         36 . The memory device of  claim 32 , further comprising:
 control circuitry configured to, during a program operation for a selected one of the memory cells, apply:
 a positive voltage to the bit line electrically connected to the selected memory cell; 
 an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; 
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; 
 a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; 
 a positive voltage to the word line electrically connected to the word line gate of the selected memory cell; and 
 a zero voltage to the word lines electrically connected to the word line gates of pairs of the memory cells not containing the selected memory cell. 
   
     
     
         37 . The memory device of  claim 36 , wherein the control circuitry is further configured to apply:
 a positive voltage or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and   a positive voltage or zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell;   
     
     
         38 . The memory device of  claim 29 , further comprising:
 control circuitry configured to, during an erase operation for a selected one of the memory cells, apply:
 a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; and 
 a negative voltage to the control gate line electrically connected to the control gate of the selected memory cell.