Semiconductor device and method for manufacturing the same

Abstract

Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a semiconductor layer;   a first electrode over and electrically connected to the semiconductor layer;   a second electrode over and electrically connected to the semiconductor layer;   a first insulating layer over the first electrode and the second electrode;   an organic resin layer over the first insulating layer; and   a pixel electrode over the organic resin layer and electrically connected to the second electrode,   wherein:   each of the first electrode and the second electrode comprises a conductive layer comprising copper;   the first insulating layer comprises silicon nitride;   the semiconductor layer comprises:
 a first region not overlapping with any of the first electrode and the second electrode; 
 a second region overlapping with the first electrode; and 
 a third region overlapping with the second electrode; 
   the first region of the semiconductor layer is positioned between the second region of the semiconductor layer and the third region of the semiconductor layer;   the first insulating layer comprises a region in contact with the first region of the semiconductor layer; and   the first region of the semiconductor layer is thinner than the second region of the semiconductor layer and the third region of the semiconductor layer.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the semiconductor layer.   
     
     
         4 . The semiconductor device according to  claim 2 , wherein the semiconductor layer is an oxide semiconductor layer. 
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein the first insulating layer comprises:
 a first layer comprising silicon oxide; and 
 a second layer over the first layer and comprising silicon nitride. 
   
     
     
         6 . The semiconductor device according to  claim 2 , comprising:
 a gate electrode; and   a second insulating layer over the gate electrode,   wherein the semiconductor layer is positioned over the second insulating layer and comprises a region overlapping with the gate electrode.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the second insulating layer.   
     
     
         8 . The semiconductor device according to  claim 6 ,
 wherein the second insulating layer comprises:
 a first layer comprising silicon nitride; and 
 a second layer over the first layer and comprising silicon oxide. 
   
     
     
         9 . A semiconductor device comprising:
 a semiconductor layer;   a first electrode over and electrically connected to the semiconductor layer;   a second electrode over and electrically connected to the semiconductor layer;   a first insulating layer over the first electrode and the second electrode;   an organic resin layer over the first insulating layer; and   a pixel electrode over the organic resin layer and electrically connected to the second electrode,   wherein:   each of the first electrode and the second electrode comprises:
 a first barrier layer; and 
 a conductive layer comprising a region in contact with the first barrier layer and comprising copper; 
   the first insulating layer comprises silicon nitride;   the semiconductor layer comprises:
 a first region not overlapping with any of the first electrode and the second electrode; 
 a second region overlapping with the first electrode; and 
 a third region overlapping with the second electrode; 
   the first region of the semiconductor layer is positioned between the second region of the semiconductor layer and the third region of the semiconductor layer;   the first insulating layer comprises a region in contact with the first region of the semiconductor layer; and   the first region of the semiconductor layer is thinner than the second region of the semiconductor layer and the third region of the semiconductor layer.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the semiconductor layer.   
     
     
         11 . The semiconductor device according to  claim 9 ,
 wherein the first barrier layer is capable of suppressing diffusion of copper.   
     
     
         12 . The semiconductor device according to  claim 9 ,
 wherein the first barrier layer comprises titanium.   
     
     
         13 . The semiconductor device according to  claim 9 ,
 wherein the first barrier layer comprises metal nitride.   
     
     
         14 . The semiconductor device according to  claim 9 ,
 wherein the semiconductor layer is an oxide semiconductor layer.   
     
     
         15 . The semiconductor device according to  claim 9 ,
 wherein the first insulating layer comprises:
 a first layer comprising silicon oxide; and 
 a second layer over the first layer and comprising silicon nitride. 
   
     
     
         16 . The semiconductor device according to  claim 9 , comprising:
 a gate electrode; and   a second insulating layer over the gate electrode,   wherein the semiconductor layer is positioned over the second insulating layer and comprises a region overlapping with the gate electrode.   
     
     
         17 . The semiconductor device according to  claim 16 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the second insulating layer.   
     
     
         18 . The semiconductor device according to  claim 16 ,
 wherein the second insulating layer comprises:
 a first layer comprising silicon nitride; and 
 a second layer over the first layer and comprising silicon oxide. 
   
     
     
         19 . A semiconductor device comprising:
 a semiconductor layer;   a first electrode over and electrically connected to the semiconductor layer;   a second electrode over and electrically connected to the semiconductor layer;   a first insulating layer over the first electrode and the second electrode;   an organic resin layer over the first insulating layer; and   a pixel electrode over the organic resin layer and electrically connected to the second electrode,   wherein:   each of the first electrode and the second electrode comprises:
 a first barrier layer; 
 a conductive layer comprising a region in contact with an upper surface of the first barrier layer and comprising copper; and 
 a second barrier layer comprising a region in contact with an upper surface of the conductive layer; 
   the first insulating layer comprises silicon nitride;   the semiconductor layer comprises:
 a first region not overlapping with any of the first electrode and the second electrode; 
 a second region overlapping with the first electrode; and 
 a third region overlapping with the second electrode; 
   the first region of the semiconductor layer is positioned between the second region of the semiconductor layer and the third region of the semiconductor layer;   the first insulating layer comprises a region in contact with the first region of the semiconductor layer; and   the first region of the semiconductor layer is thinner than the second region of the semiconductor layer and the third region of the semiconductor layer.   
     
     
         20 . The semiconductor device according to  claim 19 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the semiconductor layer.   
     
     
         21 . The semiconductor device according to  claim 19 ,
 wherein the first barrier layer is capable of suppressing diffusion of copper.   
     
     
         22 . The semiconductor device according to  claim 19 ,
 wherein the first barrier layer comprises titanium.   
     
     
         23 . The semiconductor device according to  claim 19 ,
 wherein the first barrier layer comprises metal nitride.   
     
     
         24 . The semiconductor device according to  claim 19 ,
 wherein the semiconductor layer is an oxide semiconductor layer.   
     
     
         25 . The semiconductor device according to  claim 19 ,
 wherein the first insulating layer comprises:
 a first layer comprising silicon oxide; and 
 a second layer over the first layer and comprising silicon nitride. 
   
     
     
         26 . The semiconductor device according to  claim 19 , comprising:
 a gate electrode; and   a second insulating layer over the gate electrode,   wherein the semiconductor layer is positioned over the second insulating layer and comprises a region overlapping with the gate electrode.   
     
     
         27 . The semiconductor device according to  claim 26 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the second insulating layer.   
     
     
         28 . The semiconductor device according to  claim 26 ,
 wherein the second insulating layer comprises:
 a first layer comprising silicon nitride; and 
 a second layer over the first layer and comprising silicon oxide. 
   
     
     
         29 . A semiconductor device comprising:
 a semiconductor layer;   a first electrode over and electrically connected to the semiconductor layer;   a second electrode over and electrically connected to the semiconductor layer;   a first insulating layer over the first electrode and the second electrode;   an organic resin layer over the first insulating layer; and   a pixel electrode over the organic resin layer and electrically connected to the second electrode,   wherein:   each of the first electrode and the second electrode comprises:
 a first barrier layer; 
 a conductive layer comprising a region in contact with an upper surface of the first barrier layer and comprising copper; and 
   a second barrier layer comprising a region in contact with an upper surface of the conductive layer;   the pixel electrode comprises a region in contact with an upper surface of the second barrier layer of the second electrode;   the first insulating layer comprises silicon nitride;   the semiconductor layer comprises:
 a first region not overlapping with any of the first electrode and the second electrode; 
 a second region overlapping with the first electrode; and 
 a third region overlapping with the second electrode; 
   the first region of the semiconductor layer is positioned between the second region of the semiconductor layer and the third region of the semiconductor layer;   the first insulating layer comprises a region in contact with the first region of the semiconductor layer; and   the first region of the semiconductor layer is thinner than the second region of the semiconductor layer and the third region of the semiconductor layer.   
     
     
         30 . The semiconductor device according to  claim 29 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the semiconductor layer.   
     
     
         31 . The semiconductor device according to  claim 29 ,
 wherein the first barrier layer is capable of suppressing diffusion of copper.   
     
     
         32 . The semiconductor device according to  claim 29 ,
 wherein the first barrier layer comprises titanium.   
     
     
         33 . The semiconductor device according to  claim 29 ,
 wherein the first barrier layer comprises metal nitride.   
     
     
         34 . The semiconductor device according to  claim 29 ,
 wherein the semiconductor layer is an oxide semiconductor layer.   
     
     
         35 . The semiconductor device according to  claim 29 ,
 wherein the first insulating layer comprises:
 a first layer comprising silicon oxide; and 
 a second layer over the first layer and comprising silicon nitride. 
   
     
     
         36 . The semiconductor device according to  claim 29 , comprising:
 a gate electrode; and   a second insulating layer over the gate electrode,   wherein the semiconductor layer is positioned over the second insulating layer and comprises a region overlapping with the gate electrode.   
     
     
         37 . The semiconductor device according to  claim 36 ,
 wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the second insulating layer.   
     
     
         38 . The semiconductor device according to  claim 36 ,
 wherein the second insulating layer comprises:
 a first layer comprising silicon nitride; and 
 a second layer over the first layer and comprising silicon oxide. 
   
     
     
         39 . A method for manufacturing a semiconductor device, comprising the steps of:
 forming a semiconductor layer;   forming a first conductive layer comprising copper over the semiconductor layer;   forming a resist mask over the first conductive layer;   forming a first electrode and a second electrode over the semiconductor layer by etching the first conductive layer with use of the resist mask;   forming a first insulating layer comprising a silicon nitride over the first electrode and the second electrode;   forming an organic resin layer over the first insulating layer; and   forming a pixel electrode over the organic resin layer and electrically connected to the second electrode,   wherein:   a first region of the semiconductor layer does not overlap with any of the first electrode and the second electrode;   a second region of the semiconductor layer overlaps with the first electrode;   a third region of the semiconductor layer overlaps with the second electrode;   the first region of the semiconductor layer is positioned between the second region of the semiconductor layer and the third region of the semiconductor layer;   the first region of the semiconductor layer is etched and made thinner than the second region of the semiconductor layer and the third region of the semiconductor layer while the resist mask is provided over the first electrode and the second electrode;   the first insulating layer comprises a region in contact with an upper surface of the first region of the semiconductor layer.   
     
     
         40 . The method for manufacturing a semiconductor device according to  claim 39 , further comprising the step of:
 forming a first barrier layer over the semiconductor layer,   wherein:   the first conductive layer is formed over and in contact with an upper surface of the first barrier layer;   the first electrode and the second electrode are formed by etching the first barrier layer and the first conductive layer with use of the resist mask; and   each of the first electrode and the second electrode comprises:
 a second barrier layer; and 
 a second conductive layer comprising copper and comprising a region in contact with an upper surface of the second barrier layer. 
   
     
     
         41 . The method for manufacturing a semiconductor device according to  claim 40 , wherein the first barrier layer is capable of suppressing diffusion of copper. 
     
     
         42 . The method for manufacturing a semiconductor device according to  claim 40 , wherein the first barrier layer comprises titanium. 
     
     
         43 . The method for manufacturing a semiconductor device according to  claim 40 , wherein the first barrier layer comprises a metal nitride. 
     
     
         44 . The method for manufacturing a semiconductor device according to  claim 39 , further comprising the steps of:
 forming a first barrier layer over the semiconductor layer; and   forming a second barrier layer over and in contact with an upper surface of the first conductive layer,   wherein:   the first conductive layer is formed over and in contact with an upper surface of the first barrier layer;   the resist mask is formed over the second barrier layer;   the first electrode and the second electrode are formed by etching the first barrier layer, the first conductive layer, and the second barrier layer with use of the resist mask; and   each of the first electrode and the second electrode comprises:
 a third barrier layer; 
 a second conductive layer comprising copper and comprising a region in contact with an upper surface of the third barrier layer; and 
 a fourth barrier layer comprising a region in contact with an upper surface of the second conductive layer. 
   
     
     
         45 . The method for manufacturing a semiconductor device according to  claim 44 , wherein the pixel electrode comprises a region in contact with the fourth barrier layer. 
     
     
         46 . The method for manufacturing a semiconductor device according to  claim 39 , wherein each of the first electrode and the second electrode comprise a region in contact with an upper surface of the semiconductor layer. 
     
     
         47 . The method for manufacturing a semiconductor device according to  claim 39 , wherein the semiconductor layer is an oxide semiconductor layer. 
     
     
         48 . The method for manufacturing a semiconductor device according to  claim 39 , wherein the first insulating layer comprises:
 a first layer comprising a silicon oxide; and   a second layer over the first layer and comprising a silicon nitride.   
     
     
         49 . The method for manufacturing a semiconductor device according to  claim 39 , wherein:
 a lower end portion of the first electrode comprises a region in contact with an upper end portion of the second region of the semiconductor layer; and   a lower end portion of the second electrode comprises a region in contact with an upper end portion of the third region of the semiconductor layer.   
     
     
         50 . The method for manufacturing a semiconductor device according to  claim 39 , further comprising the steps of:
 forming a gate electrode; and   forming a second insulating layer over the gate electrode,   wherein the semiconductor layer is formed over the second insulating layer and comprises a region overlapping with the gate electrode.   
     
     
         51 . The method for manufacturing a semiconductor device according to  claim 50 , wherein each of the first electrode and the second electrode comprises a region in contact with an upper surface of the second insulating layer. 
     
     
         52 . The method for manufacturing a semiconductor device according to  claim 50 , wherein the second insulating layer comprises:
 a third layer comprising a silicon nitride; and   a fourth layer over the third layer and comprising a silicon nitride.