Manufacturing method of display substrate, display substrate and display device

Abstract

A manufacturing method of a display substrate, a display substrate, and a display device are disclosed. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

What is claimed is: 
     
         1 . A manufacturing method of a display substrate, comprising manufacturing a top-gate type thin film transistor on a side of a base substrate, wherein manufacturing the top-gate type thin film transistor on the side of the base substrate comprises:
 forming an active layer;   forming a gate insulation film layer, a gate film layer and a photoresist film layer sequentially on a side of the active layer away from the base substrate;   exposing the photoresist film layer to a light using a mask as a protection mask, and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle that is not less than 70°;   over-etching the gate film layer to form a gate electrode using the developed photoresist film layer as a protection mask, an orthographic projection of the gate electrode on the base substrate being located within a region of an orthographic projection of the developed photoresist film layer on the base substrate;   over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer using the developed photoresist film layer as a protection mask;   peeling off the photoresist film layer remaining on a surface of the gate electrode; and   performing a conductive treatment to the active layer using the gate insulation layer as a protection mask.   
     
     
         2 . The manufacturing method according to  claim 1 , wherein exposing the photoresist film layer to the light comprises:
 without exposing a region of the photoresist film layer corresponding to the gate electrode to be formed, fully exposing a region corresponding to an etched region of the gate film layer to the light.   
     
     
         3 . The manufacturing method according to  claim 1 , wherein the gate insulation film layer is over-etched for an over-etching time of (20%˜30%)*t by the gaseous corrosion method, where t is a normal time period during which the gate insulation film layer is etched to a predetermined depth. 
     
     
         4 . The manufacturing method according to  claim 1 , wherein a gas atmosphere of the gaseous corrosion comprises carbon tetrafluoride (CF 4 ) at a flow rate of 2000 to 2500 Standard Cubic Centimeters per Minute (SCCM) and oxygen (O 2 ) at a flow rate of 200 to 650 SCCM. 
     
     
         5 . The manufacturing method according to  claim 1 , wherein an edge of the orthographic projection of the gate electrode on the base substrate is spaced apart from an edge of the orthographic projection of the developed photoresist film layer on the base substrate by 1 to 1.5 μm. 
     
     
         6 . The manufacturing method according to  claim 1 , wherein before the step of forming the active layer, the manufacturing method further comprises:
 forming a light shielding layer on the base substrate, the active layer being opposite to the light shielding layer; and   forming a first insulation layer covering the light shielding layer on a side of the light shielding layer away from the base substrate.   
     
     
         7 . The manufacturing method according to  claim 6 , further comprising:
 forming a second insulation layer on a side of the gate electrode away from the base substrate.   
     
     
         8 . The manufacturing method according to  claim 7 , further comprising:
 forming a first via hole and a second via hole communicated to the active layer which has been subjected to the conductive treatment, orthographic projections of the first via hole and the second via hole on the base substrate being respectively located at two opposite sides of the orthographic projection of the gate electrode on the base substrate.   
     
     
         9 . The manufacturing method according to  claim 8 , further comprising:
 forming a source electrode and a drain electrode on a side of the second insulation layer away from the base substrate, the source electrode and the drain electrode being connected to the active layer which has been subjected to the conductive treatment respectively through the first via hole and the second via hole.   
     
     
         10 . The manufacturing method according to  claim 9 , further comprising:
 forming a third via hole communicated to the first insulation layer, an orthographic projection of the third via hole on the base substrate being spaced apart from an orthographic projection of the active layer on the base substrate.   
     
     
         11 . The manufacturing method according to  claim 10 , further comprising:
 forming a fourth via hole communicated to the light shielding layer, an orthographic projection of the fourth via hole on the base substrate coinciding with the orthographic projection of the third via hole on the base substrate, and the light shielding layer being connected to the source electrode or the drain electrode through the fourth via hole and the third via hole.   
     
     
         12 . The manufacturing method according to  claim 11 , wherein the fourth via hole, the first via hole and the second via hole are formed by one patterning process. 
     
     
         13 . The manufacturing method according to  claim 9 , wherein after forming the source electrode and the drain electrode on the side of the second insulation layer away from the base substrate, the manufacturing method further comprises:
 forming a passivation layer on a side of the source electrode and the drain electrode away from the base substrate.   
     
     
         14 . The manufacturing method according to  claim 1 , further comprising:
 forming a second insulation layer on a side of the gate electrode away from the base substrate;   forming a first via hole and a second via hole communicated to the active layer which has been subjected to the conductive treatment, orthographic projections of the first via hole and the second via hole on the base substrate being respectively located at two sides of the orthographic projection of the gate electrode on the base substrate; and   forming a source electrode and a drain electrode on a side of the second insulation layer away from the base substrate, the source electrode and the drain electrode being connected to the active layer which has been subjected to the conductive treatment respectively through the first via hole and the second via hole.   
     
     
         15 . The manufacturing method according to  claim 6 , further comprising:
 forming a third via hole communicated to the first insulation layer, an orthographic projection of the third via hole on the base substrate being spaced apart from an orthographic projection of the active layer on the base substrate; and   forming a fourth via hole communicated to the light shielding layer, an orthographic projection of the fourth via hole on the base substrate coinciding with the orthographic projection of the third via hole on the base substrate.   
     
     
         16 . The manufacturing method according to  claim 14 , wherein after forming the source electrode and the drain electrode on the side of the second insulation layer away from the base substrate, the manufacturing method further comprises:
 forming a passivation layer on a side of the source electrode and the drain electrode away from the base substrate.   
     
     
         17 . A display substrate manufactured by the manufacturing method of the display substrate according to  claim 1 . 
     
     
         18 . A display substrate manufactured by the manufacturing method of the display substrate according to  claim 2 . 
     
     
         19 . A display substrate manufactured by the manufacturing method of the display substrate according to  claim 3 . 
     
     
         20 . A display device, comprising the display substrate according to  claim 17 .