Vertical FET with Sharp Junctions

Abstract

VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.

What is claimed is: 
     
         1 . A vertical field-effect transistor (VFET) device, comprising:
 a substrate;   a silicon germanium (SiGe) layer disposed on the substrate;   fins disposed on the SiGe layer, wherein the fins comprise undoped silicon (Si);   recesses in the SiGe layer between the fins; and   an epitaxial material in the recesses that comprises a source and drain dopant,   wherein the SiGe layer under the fins also comprises the source and drain dopant and forms bottom source and drains of the VFET device.   
     
     
         2 . The VFET device of  claim 1 , wherein the source and drain dopant comprises phosphorous (P). 
     
     
         3 . The VFET device of  claim 2 , wherein the epitaxial material in the recesses is selected from the group consisting of: Si:P and Si:C(P). 
     
     
         4 . The VFET device of  claim 1 , wherein the source and drain dopant comprises boron (B). 
     
     
         5 . The VFET device of  claim 4 , wherein the epitaxial material in the recesses comprises SiGe:B. 
     
     
         6 . The VFET device of  claim 1 , wherein the epitaxial material in the recesses comprises the source and drain dopant at a concentration of from about 4×10 20  atoms/cm 3  to about 2×10 21  atoms/cm 3  and ranges therebetween. 
     
     
         7 . The VFET device of  claim 1 , further comprising:
 a bottom spacer disposed on the bottom source and drains;   a gate dielectric disposed on sidewalls of the fins and the bottom spacer;   a gate conductor disposed on the gate dielectric;   an organic planarizing layer (OPL) surrounding the fins;   a top spacer disposed on the OPL in between the tops of the fins; and   top source and drains of the VFET device formed on the tops of the fins,   wherein the fins between the bottom source and drains and the top source and drains comprise vertical fin channels of the VFET device.   
     
     
         8 . The VFET device of  claim 7 , wherein a top of the OPL is below tops of the fins. 
     
     
         9 . The VFET device of  claim 7 , wherein the gate dielectric comprises a high-κ dielectric selected from the group consisting of: hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), and combinations thereof. 
     
     
         10 . The VFET device of  claim 7 , wherein the gate conductor comprises a workfunction setting metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), an aluminum (Al)-containing alloy, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), and combinations thereof. 
     
     
         11 . The VFET device of  claim 7 , wherein the bottom spacer and the top spacer each comprises a material selected from the group consisting of: silicon oxide (SiO 2 ), SiN, and combinations thereof. 
     
     
         12 . The VFET device of  claim 7 , wherein the top source and drains comprise SiGe:P. 
     
     
         13 . The VFET device of  claim 7 , wherein the top source and drains comprise SiGe:B. 
     
     
         14 . A VFET device, comprising:
 a substrate;   a SiGe layer disposed on the substrate;   fins disposed on the SiGe layer, wherein the fins comprise undoped Si;   recesses in the SiGe layer between the fins;   an epitaxial material in the recesses that comprises a source and drain dopant, wherein the SiGe layer under the fins also comprises the source and drain dopant and forms bottom source and drains of the VFET device;   a bottom spacer disposed on the bottom source and drains;   a gate dielectric disposed on sidewalls of the fins and the bottom spacer;   a gate conductor disposed on the gate dielectric;   an OPL surrounding the fins;   a top spacer disposed on the OPL in between the tops of the fins; and   top source and drains of the VFET device formed on the tops of the fins, wherein the fins between the bottom source and drains and the top source and drains comprise vertical fin channels of the VFET device.   
     
     
         15 . The VFET device of  claim 14 , wherein the source and drain dopant comprises phosphorous (P). 
     
     
         16 . The VFET device of  claim 15 , wherein the epitaxial material in the recesses is selected from the group consisting of: Si:P and Si:C(P). 
     
     
         17 . The VFET device of  claim 14 , wherein the source and drain dopant comprises boron (B). 
     
     
         18 . The VFET device of  claim 17 , wherein the epitaxial material in the recesses comprises SiGe:B. 
     
     
         19 . The VFET device of  claim 14 , wherein the epitaxial material in the recesses comprises the source and drain dopant at a concentration of from about 4×10 20  atoms/cm 3  to about 2×10 21  atoms/cm 3  and ranges therebetween. 
     
     
         20 . The VFET device of  claim 14 , wherein a top of the OPL is below tops of the fins.