Transistors with dielectric-isolated source and drain regions

Abstract

Semiconductor devices include a semiconductor layer comprising a channel region and source/drain regions. A gate stack is formed on the channel region. A dielectric layer is formed on the semiconductor layer in the source/drain regions. Source/drain structures are formed over the dielectric layer in the source/drain regions.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor layer comprising a channel region and source/drain regions;   a gate stack formed on the channel region;   a dielectric layer formed on the semiconductor layer in the source/drain regions; and   source/drain structures formed over the dielectric layer in the source/drain regions.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a layer of sacrificial material below the dielectric layer in the recesses. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the dielectric layer is formed from silicon dioxide and the sacrificial layer is formed from silicon germanium. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a surface of the semiconductor layer has a crystalline orientation of <100>. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the channel region of the fin has a height greater than the source/drain regions of the fin. 
     
     
         6 . The semiconductor device of  claim 5 , wherein a shallow-trench isolation dielectric comes to a height greater than the height of the source/drain regions of the fin. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the source/drain structures are epitaxially grown semiconductor structures. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the source/drain structures have a trapezoidal cross-section. 
     
     
         9 . The semiconductor device of  claim 1 , wherein a bottom surface of the source/drain structures has a height lower than a top surface of the semiconductor layer. 
     
     
         10 . A planar semiconductor device, comprising:
 a bulk semiconductor substrate comprising a channel region and source/drain regions;   a gate stack formed on the channel region of the bulk semiconductor substrate;   a dielectric layer formed in recesses in the source/drain regions of the bulk semiconductor substrate; and   source/drain structures formed over the dielectric layer in the source/drain regions of the bulk semiconductor substrate.   
     
     
         11 . The semiconductor device of  claim 10 , further comprising a layer of sacrificial material below the dielectric layer in the recesses. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the dielectric layer is formed from silicon dioxide and the sacrificial layer is formed from silicon germanium. 
     
     
         13 . The semiconductor device of  claim 10 , wherein a bottom surface of the recesses has a crystalline orientation of <100> and wherein other facets of the recesses have a crystalline orientation of <111>. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the source/drain structures have a trapezoidal cross-section. 
     
     
         15 . The semiconductor device of  claim 10 , wherein a bottom surface of the source/drain structures has a height lower than a top surface of the bulk semiconductor substrate. 
     
     
         16 . A fin semiconductor device, comprising:
 a fin formed from a bulk semiconductor substrate, comprising a channel region and source/drain regions;   a gate stack formed on the channel region of the fin;   a dielectric layer formed on the source/drain regions of the fin; and   source/drain structures formed over the dielectric layer.   
     
     
         17 . The semiconductor device of  claim 16 , further comprising a layer of sacrificial material between the dielectric layer and the fin. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the dielectric layer is formed from silicon dioxide and the sacrificial layer is formed from silicon germanium. 
     
     
         19 . The semiconductor device of  claim 16 , wherein the channel region of the fin has a height greater than the source/drain regions of the fin. 
     
     
         20 . The semiconductor device of  claim 19 , wherein a shallow-trench isolation dielectric comes to a height greater than the height of the source/drain regions of the fin.