System, apparatus, and method of programming a one-time programmable memory circuit

Abstract

A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

What is claimed is: 
     
         1 . A method of programming a gate device, comprising:
 applying a gate to source voltage of approximately −3 volts to a programmable gate device;   applying a first program voltage of approximately −1.4 volts to a drain side Vt program region of the programmable gate device; and   applying a second program voltage of approximately −1.4 volts to a source side Vt program region of the programmable gate device.   
     
     
         2 . The method of  claim 1 , wherein the programmable gate device has a 5 nm to 10 nm channel length. 
     
     
         3 . The method of  claim 1 , wherein the programmable gate device is a one-time programmable device. 
     
     
         4 . The method of  claim 3 , wherein applying the first program voltage creates a first charge trap between a drain and a gate of the programmable gate device. 
     
     
         5 . The method of  claim 4 , wherein applying the second program voltage creates a second charge trap between a source and the gate of the programmable gate device. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the dual program creates a first charge trap between a drain and a gate and a second charge trap between a source and the gate of the programmable gate device. 
     
     
         7 . The method of  claim 1 , further comprising integrating the gate device into one of a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem. 
     
     
         8 . An apparatus for programming a gate device, comprising:
 at least one program circuit configured to:
 apply a gate to source voltage of approximately −3 volts to a programmable gate device; 
 apply a first program voltage of approximately −1.4 volts to a drain side Vt program region of the programmable gate device; and 
 apply a second program voltage of approximately −1.4 volts to a source side Vt program region of the programmable gate device. 
   
     
     
         9 . The apparatus of  claim 8 , wherein the programmable gate device has a 5 nm to 10 nm channel length. 
     
     
         10 . The apparatus of  claim 8 , wherein the programmable gate device is a one-time programmable device. 
     
     
         11 . The apparatus of  claim 10 , wherein application of the first program voltage creates a first charge trap between a drain and a gate of the programmable gate device. 
     
     
         12 . The apparatus of  claim 11 , wherein application of the second program voltage creates a second charge trap between a source and the gate of the programmable gate device. 
     
     
         13 . The apparatus of  claim 8 , wherein the dual program creates a first charge trap between a drain and a gate and a second charge trap between a source and the gate of the programmable gate device. 
     
     
         14 . The apparatus of  claim 8 , wherein the gate device is integrated into one of a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, or a wireless modem. 
     
     
         15 . A non-transitory computer-readable medium storing computer-executable instructions for programming a gate device, the computer-executable instructions comprising:
 at least one instruction for applying a gate to source voltage of approximately −3 volts to a programmable gate device;   at least one instruction for applying a first program voltage of approximately −1.4 volts to a drain side Vt program region of the programmable gate device; and   at least one instruction for applying a second program voltage of approximately −1.4 volts to a source side Vt program region of the programmable gate device.   
     
     
         16 . The non-transitory computer-readable medium of  claim 15 , wherein the programmable gate device has a 5 nm to 10 nm channel length. 
     
     
         17 . The non-transitory computer-readable medium of  claim 15 , wherein the programmable gate device is a one-time programmable device. 
     
     
         18 . The non-transitory computer-readable medium of  claim 17 , wherein application of the first program voltage creates a first charge trap between a drain and a gate of the programmable gate device. 
     
     
         19 . The non-transitory computer-readable medium of  claim 18 , wherein application of the second program voltage creates a second charge trap between a source and the gate of the programmable gate device. 
     
     
         20 . The non-transitory computer-readable medium of  claim 15 , wherein the dual program creates a first charge trap between a drain and a gate and a second charge trap between a source and the gate of the programmable gate device.