Write verify programming of a memory device

Abstract

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

1 - 20 . (canceled) 
     
     
         21 . A method comprising:
 receiving, at a memory device, data targeted for storage in a plurality of bit cells of a memory array, wherein each bit cell of the plurality of bit cells is configured to be in one of a first state or a second state;   identifying, based at least in part on the received data, a first set of bit cells of the plurality of bit cells to be placed in the first state, and identifying a second set of bit cells of the plurality bit cells to be placed in the second state;   applying a first voltage to the first set of bit cells to change a portion of bit cells in the first set of bit cells to the first state, wherein the first voltage includes a first magnitude and a first duration;   applying a second voltage to the second set of bit cells to change a portion of bit cells in the second set of bit cells to the second state, wherein the second voltage includes a second magnitude and a second duration;   identifying a first subset of bit cells from the first set of bit cells, wherein the first subset of bit cells contains each bit cell in the first set that remains in the second state, and identifying a second subset of bit cells from the second set of bit cells, wherein the second subset of bit cells contains each bit cell in the second set that remains in the first state;   applying a third voltage to each bit cell of the first subset of bit cells to change each bit cell of the first subset of bit cells from the second state to the first state, wherein the third voltage includes a third magnitude and a third duration, and wherein at least one of the third magnitude and the third duration is greater than the first magnitude and the first duration, respectively; and   applying a fourth voltage to each bit cell of the second subset of bit cells to change each bit cell of the second subset of bit cells from the first state to the second state, wherein the fourth voltage includes a fourth magnitude and a fourth duration, and wherein at least one of the fourth magnitude and the fourth duration is greater than the second magnitude and the second duration, respectively.   
     
     
         22 . The method of  claim 21 , wherein the data targeted for storage in the plurality of bit cells is accessed from a cache in response to a precharge command, a command issued to the memory device from an external device, or a command issued internally by the memory device. 
     
     
         23 . The method of  claim 21 , wherein the magnitude or duration of the third voltage is configured to set each bit cell of the first subset of bit cells to the first state; and
 wherein the magnitude or duration of the fourth voltage is configured to set each bit cell of the second subset of bit cells to the second state.   
     
     
         24 . The method of  claim 21 , wherein the first state is a high resistive state, and the second state is a low resistive state. 
     
     
         25 . The method of  claim 21 , wherein the first state is a low resistive state, and the second state is a high resistive state. 
     
     
         26 . The method of  claim 21 , wherein one or more of the identifying steps includes sampling a state of each bit cell of the plurality of bit cells. 
     
     
         27 . The method of  claim 21 , wherein the first voltage is applied in a first direction, and the second voltage is applied in a second direction opposite to the first direction; and
 wherein each bit cell of the plurality of bit cells is a magnetic tunnel junction.   
     
     
         28 . The method of  claim 21 , wherein identifying the first set of bit cells, identifying the second set of bit cells, identifying the first subset of bit cells, and/or identifying the second subset of bit cells includes a referenced read operation. 
     
     
         29 . A method comprising:
 receiving, at a memory device, data targeted for storage in a plurality of bit cells of a memory array, wherein each bit cell of the plurality of bit cells is configured to be in one of a first state or a second state;   identifying, based at least in part on the received data, a first set of bit cells of the plurality of bit cells to be placed in the first state, and identifying a second set of bit cells of the plurality bit cells to be placed in the second state;   applying a first voltage to the first set of bit cells to change a portion of bit cells in the first set of bit cells to the first state, wherein the first voltage includes a first magnitude and a first duration;   applying a second voltage to the second set of bit cells to change a portion of bit cells in the second set of bit cells to the second state.   
     
     
         30 . The method of  claim 29 , wherein the data targeted for storage in the plurality of bit cells is accessed from a cache in response to a precharge command, a command issued to the memory device from an external device, or a command issued internally by the memory device. 
     
     
         31 . The method of  claim 29 , wherein the first state is a high resistive state, and the second state is a low resistive state. 
     
     
         32 . The method of  claim 29 , wherein the first state is a low resistive state, and the second state is a high resistive state. 
     
     
         33 . The method of  claim 29 , wherein the identifying step includes sampling a state of each bit cell of the plurality of bit cells. 
     
     
         34 . The method of  claim 29 , wherein the first voltage is applied in a first direction, and the second voltage is applied in a second direction opposite to the first direction; and
 wherein each bit cell of the plurality of bit cells is a magnetic tunnel junction.   
     
     
         35 . The method of  claim 29 , wherein identifying the first set of bit cells and identifying the second set of bit cells includes a referenced read operation. 
     
     
         36 . The method of  claim 29 , wherein the second voltage includes a second magnitude and a second duration, wherein the second magnitude is different from the first magnitude and the second duration is different from the first duration
 and wherein the method further comprises:   identifying a first subset of bit cells from the first set of bit cells, wherein the first subset of bit cells contains each bit cell in the first set that remains in the second state, and identifying a second subset of bit cells from the second set of bit cells, wherein the second subset of bit cells contains each bit cell in the second set that remains in the first state;   applying a third voltage to each bit cell of the first subset of bit cells to change each bit cell of the first subset of bit cells from the second state to the first state, wherein the third voltage includes a third magnitude and a third duration, and wherein at least one of the third magnitude and the third duration is greater than the first magnitude and the first duration, respectively; and   applying a fourth voltage to each bit cell of the second subset of bit cells to change each bit cell of the second subset of bit cells from the first state to the second state, wherein the fourth voltage includes a fourth magnitude and a fourth duration, and wherein at least one of the fourth magnitude and the fourth duration is greater than the second magnitude and the second duration, respectively.   wherein the magnitude or duration of the third voltage is configured to set each bit cell of the first subset of bit cells to the first state; and   wherein the magnitude or duration of the fourth voltage is configured to set each bit cell of the second subset of bit cells to the second state.   
     
     
         37 . A method comprising:
 receiving, at a memory device, data targeted for storage in a plurality of bit cells of a memory array, wherein each bit cell of the plurality of bit cells is configured to be in one of a first state or a second state;   identifying, based at least in part on the received data, a first set of bit cells of the plurality of bit cells to be placed in the first state;   applying a first voltage to the first set of bit cells to change a portion of bit cells in the first set of bit cells to the first state, wherein the first voltage includes a first magnitude and a first duration;   identifying a first subset of bit cells from the first set of bit cells, wherein the first subset of bit cells contains each bit cell in the first set that remains in the second state; and   applying a second voltage to each bit cell of the first subset of bit cells to change each bit cell of the first subset of bit cells from the second state to the first state, wherein the second voltage includes a second magnitude and a second duration, and wherein at least one of the second magnitude and the second duration is greater than the first magnitude and the first duration, respectively.   
     
     
         38 . The method of  claim 37 , wherein the data targeted for storage in the plurality of bit cells is accessed from a cache in response to a precharge command, a command issued to the memory device from an external device, or a command issued internally by the memory device. 
     
     
         39 . The method of  claim 37 , wherein each bit cell of the plurality of bit cells is a magnetic tunnel junction; and
 wherein identifying the first set of bit cells and/or identifying the first subset of bit cells includes a referenced read operation.   
     
     
         40 . The method of  claim 37 , further comprising: identifying a second set of bit cells of the plurality bit cells to be placed in the second state;
 applying a third voltage to the second set of bit cells to change a portion of bit cells in the second set of bit cells to the second state, wherein the third voltage includes a third magnitude and a third duration;   identifying a second subset of bit cells from the second set of bit cells, wherein the second subset of bit cells contains each bit cell in the second set that remains in the first state; and   applying a fourth voltage to each bit cell of the second subset of bit cells to change each bit cell of the second subset of bit cells from the first state to the second state, wherein the fourth voltage includes a fourth magnitude and a fourth duration, and wherein at least one of the fourth magnitude and the fourth duration is greater than the third magnitude and the third duration, respectively.