Scalable Coherent Apparatus and Method

Abstract

Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system.

What is claimed is: 
     
         1 . A scalable coherent communications method comprising:
 using a first directory cache coherent directory implemented within an on-chip cache coherent fabric to track coherency between on-chip cores; and   using a second directory cache coherent directory implemented within an on-chip module to keep track of participating on-chip cores.   
     
     
         2 . The method of  claim 1  wherein said first directory maintains an on-chip coherent cache directory to keep track of cache lines and states, and maintains transaction ordering for no-chip coherent cache participants; and performs memory transaction processing. 
     
     
         3 . The method of  claim 2  wherein said second directory maintains a scale-out coherent cache directory for participating processing elements, performs transaction ordering and flow control; and processes both coherent and non-coherent transactions. 
     
     
         4 . The method of  claim 3  wherein said second directory performs an ACE-RapidIO mapping. 
     
     
         5 . The method of  claim 4  wherein said second directory performs an AXI ID to transaction ID mapping for coherency extension. 
     
     
         6 . The method of  claim 4  wherein said second directory performs an ARM QoS to {prio, crf} field mapping. 
     
     
         7 . A system on a chip (SoC) apparatus comprising:
 an on-chip cache coherent interconnect connected to a plurality of cores, the on-chip cache coherent interconnect maintaining an on-chip cache coherency directory, maintaining transaction ordering for all on-chip cache coherent participating cores from the plurality of cores; and   an external interface block connected to the on-chip cache coherent interconnect;   wherein the external interface block maintains a scale-out cache coherency directory, maintains transaction order and flow control information, and handles off-chip RapidIO transaction processing.   
     
     
         8 . The system of  claim 7  wherein the external interface block is connected to a RapidIO switch. 
     
     
         9 . The system of  claim 8  wherein the RapidIO switch is connected to a plurality of processing elements.