Embedded Flash Memory Device with Floating Gate Embedded in a Substrate

Abstract

An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

What is claimed is: 
     
         1 . A method comprising:
 recessing a semiconductor portion of a semiconductor substrate to form a recess in an entirety of a first memory array region of the semiconductor substrate, the semiconductor substrate having an upper surface in a non-recessed region of the semiconductor substrate, wherein a bottom surface of the recess is a surface of the semiconductor substrate;   depositing a bottom dielectric layer on the bottom surface of the recess;   forming a charge storage layer over the bottom dielectric layer, wherein a portion of the charge storage layer is in the recess;   planarizing the charge storage layer and the bottom dielectric layer;   forming a top dielectric layer over the charge storage layer, the top dielectric layer being above the upper surface of the semiconductor substrate;   forming a metal gate over the top dielectric layer; and   forming a source region and a drain region in the bottom surface of the recess in the semiconductor substrate and on opposite sides of the charge storage layer to form a memory device, wherein an array of memory devices is formed in the first memory array region when the memory device is formed.   
     
     
         2 . The method of  claim 1 , wherein the top dielectric layer is a composite layer comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming a gate spacer contacting both the charge storage layer and the metal gate, wherein the gate spacer comprises a portion extending into the recess.   
     
     
         4 . The method of  claim 1 , further comprising forming an inter-layer dielectric extending into the recess. 
     
     
         5 . The method of  claim 1 , further comprising forming a gate spacer, wherein the gate spacer contacts the charge storage layer and the bottom dielectric layer. 
     
     
         6 . The method of  claim 1 , wherein an entirety of a topmost surface of the top dielectric layer is above the top surface of the semiconductor substrate. 
     
     
         7 . The method of  claim 1 , further comprising:
 before forming the metal gate, forming a dummy gate layer over the top dielectric layer.   
     
     
         8 . The method of  claim 7 , further comprising after forming the dummy gate layer:
 forming a gate spacer; and   removing the dummy gate layer.   
     
     
         9 . A method comprising:
 etching a semiconductor substrate to form a recess extending into the semiconductor substrate; and   forming an embedded flash memory device comprising:
 forming a bottom dielectric layer comprising:
 a first horizontal portion over a top surface of the semiconductor substrate; 
 a second horizontal portion in the recess; and 
 a vertical portion connecting the first horizontal portion with the second horizontal portion; 
 
 forming a charge storage layer over the bottom dielectric layer, with a portion of the charge storage layer in the recess; 
 performing a planarization to level a top surface of the charge storage layer with a top surface of the bottom dielectric layer; 
 forming a top dielectric layer over the charge storage layer; 
 forming a metal gate over the top dielectric layer; 
 patterning to remove the first horizontal portion of the bottom dielectric layer; and 
 forming a source region and a drain region in the semiconductor substrate and on opposite sides of the charge storage layer. 
   
     
     
         10 . The method of  claim 9 , wherein the source region and the drain region are isolated from each other by a channel of the embedded flash memory device, and the source region and the drain region extend from a bottom surface of the recessed semiconductor substrate into the semiconductor substrate. 
     
     
         11 . The method of  claim 9  further comprising:
 after forming the metal gate, forming a gate spacer, the gate spacer comprising a first edge contacting the bottom dielectric layer and the charge storage layer. 
 
     
     
         12 . The method of  claim 11 , wherein the first edge of the gate spacer further contacts the top dielectric layer and the metal gate. 
     
     
         13 . The method of  claim 9 , wherein the embedded flash memory device is comprised in a memory array comprising a plurality of embedded flash memory devices, and wherein an intermediate portion of the semiconductor substrate between two neighboring ones of the plurality of embedded flash memory devices remains after the recess is formed. 
     
     
         14 . The method of  claim 9 , wherein the embedded flash memory device is comprised in a memory array comprising a plurality of embedded flash memory devices, and wherein an intermediate portion of the semiconductor substrate between two neighboring ones of the plurality of embedded flash memory devices is part of the recessed semiconductor substrate. 
     
     
         15 . The method of  claim 9 , wherein the patterning to remove the first horizontal portion of the bottom dielectric layer further comprises removing the vertical portion of the bottom dielectric layer. 
     
     
         16 . A method comprising:
 etching a recess into a semiconductor substrate;   blanket depositing a bottom dielectric layer, the bottom dielectric layer comprising:
 a first horizontal portion of the bottom dielectric layer in the recess; 
 a second horizontal portion of the bottom dielectric layer over a non-recessed portion of the semiconductor substrate; and 
 a vertical portion of the bottom dielectric layer connecting the first horizontal portion with the second horizontal portion; 
   forming a charge storage layer over the bottom dielectric layer, wherein a first portion of the charge storage layer is in the recess and a second portion of the charge storage layer is over the non-recessed portion of the semiconductor substrate;   forming a top dielectric layer over the charge storage layer; and   patterning the charge storage layer and the bottom dielectric layer to form a plurality of charge storage layers and a plurality of bottom dielectric layers for a plurality of embedded memory devices, the patterning removing the vertical portion of the bottom dielectric layer.   
     
     
         17 . The method of  claim 16 , further comprising forming other semiconductor devices in a non-recessed device region, the non-recessed device region being located on the non-recessed portion of the semiconductor substrate. 
     
     
         18 . The method of  claim 16 , further comprising:
 before patterning the charge storage layer and the bottom dielectric layer, forming a dummy gate layer over the top dielectric layer.   
     
     
         19 . The method of  claim 18 , further comprising, after patterning the charge storage layer and the bottom dielectric layer:
 removing the dummy gate layer; and   forming a metal gate over the top dielectric layer.   
     
     
         20 . The method of  claim 19 , wherein the top dielectric layer is a composite layer comprising a silicon oxide layer and a silicon nitride layer.