Cell Structure for Dual-Port SRAM

Abstract

The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.

What is claimed is: 
     
         1 . A static random access memory (SRAM) cell including a plurality of fin field-effect transistors (FINFETs), the SRAM cell comprising:
 a first fin and a second fin on a semiconductor substrate in a first well region, wherein each of the first and second fins includes source, channel, and drain regions of a pull-up FINFET associated with at least one of the first and second fins;   a third fin on the semiconductor substrate in a second well region, wherein the third fin includes source, channel, and drain regions of a pull-down FINFET associated with the third fin, wherein the third fin is spaced apart from a first side of the first and second fins;   a fourth fin on the semiconductor substrate in the second well region, wherein the fourth fin includes source, channel, and drain regions of a pull-down FINFET associated with the fourth fin, wherein the fourth fin is spaced apart from a second side opposite to the first side of the first and second fins, wherein the first, second, third, and fourth fins extend in a first direction;   a first gate layer formed on at least one of the first and second fins and at least one of the third and fourth fins, wherein the first gate layer includes gate regions of a pull-down FINFET associated with at least one of the first and second fins;   a second gate layer formed on at least one the first, second, and fourth fins, wherein the second gate layer includes gate regions of at least one pull-down FINFET and at least one pull-up FINFET associated with at least one of the first, second, and fourth fins;   a third gate layer formed on the third fin, wherein the third gate layer includes gate regions of at least one pass gate FINFET associated with the third fin;   a fourth gate layer formed on the fourth fin, wherein the fourth gate layer includes gate regions of at least one pass gate FINFET associated with the fourth fin, wherein the first, second, third and fourth gate layers extend in a second direction perpendicular to the first direction;   a first contact feature formed on the third and fourth fins between the first and third gate layers, wherein the first contact feature extends in the second direction; and   a second contact feature formed on the first fin for connecting the first contact feature with the second gate layer, wherein the second contact feature extends in the first direction.   
     
     
         2 . The SRAM cell of  claim 1 , wherein the first well region is one of a n-well region and a p-well region and the second well region is another one of the n-well region and the p-well region. 
     
     
         3 . The SRAM cell of  claim 1 , wherein the first gate layer is formed on the first fin and the second gate layer is formed on the second fin. 
     
     
         4 . The SRAM cell of  claim 1 , wherein, along the second direction, each of the contact features has a dimension greater than a dimension of the fin where the respective contact feature is formed on. 
     
     
         5 . The SRAM cell of  claim 1 , further comprising:
 a third contact feature on the first fin for connecting to a first power line; and   a fourth contact feature on the second fin for connecting to the first power line.   
     
     
         6 . The SRAM cell of  claim 5 , wherein the first power line connects to one of VCC and VSS and a second power line connects to another one of VCC and VSS. 
     
     
         7 . The SRAM cell of  claim 1 , further comprising a read port that includes at least two pull-down FINFETs in parallel and at least two pass gate FINFETs in parallel. 
     
     
         8 . The SRAM cell of  claim 1 , further comprising a first common region on the third fin defined by the source and drain regions of a pull down FINFET and a pass gate FINFET associated with the third fin connected in series therethrough. 
     
     
         9 . The SRAM cell of  claim 8 , further comprising a second common region on the fourth fin defined by the source and drain regions of a pull down FINFET and a pass gate FINFET associated with the fourth fin connected in series therethrough. 
     
     
         10 . The SRAM cell of  claim 9 , wherein the first contact feature is formed on the first common region and the second contact feature is formed on the second common region. 
     
     
         11 . A static random access memory (SRAM) cell including a plurality of fin field-effect transistors (FINFETs), the SRAM cell comprising:
 a first fin on a semiconductor substrate in an n-well region;   second, third, fourth, and fifth fins on the semiconductor substrate in a p-well region;   a sixth fin on the semiconductor substrate in the n-well region;   seventh, eighth, ninth, and tenth fins on the semiconductor substrate in another p-well region, wherein the first fin and the seventh through tenth fins are on opposite sides of the sixth fin, wherein the first through tenth fins are distributed along a first direction and oriented along a second direction that is perpendicular to the first direction,
 wherein the first fin includes source, channel, and drain regions of a first pull-up FINFET, 
 wherein the second, third, and fourth fins include source, channel, and drain regions of first, second, third pull-down FINFETs, respectively, 
 wherein the third fin further includes source, channel, and drain regions of a first pass gate FINFET, 
 wherein the fifth fin includes source, channel, and drain regions of a second pass gate FINFET, 
 wherein the sixth fin includes source, channel, and drain regions of a second pull-up FINFET, 
 wherein the seventh, eighth, and ninth fins include source, channel, and drain regions of fourth, fifth, and sixth pull-down FINFETs respectively, and the eighth fin further includes source, channel, and drain regions of a third pass gate FINFET, 
 wherein the tenth fin includes source, channel, and drain regions of a fourth pass gate FINFET; 
   a first contact feature that electrically connects to the drain region of the first pull-up FINFET;   a second contact feature that electrically connects to the second pull-up FINFET; and   
       a read port that includes at least two pull-down FINFETs and at least two pass gate FINFETs. 
     
     
         12 . The SRAM cell of  claim 11 , further comprising:
 a first gate electrode oriented in the first direction and over the channel regions of the first pull-up FINFET and the first, second, and third pull-down FINFETs;   a second gate electrode oriented in the first direction and over the channel regions of the second pull-up FINFET and the fourth, fifth, and sixth pull-down FINFETs;   a third gate electrode oriented in the first direction and over the channel regions of the first and second pass gate FINFETs; and   a fourth gate electrode oriented in the first direction and over the channel regions of the third and fourth pass gate FINFETs.   
     
     
         13 . The SRAM cell of  claim 12 , further comprising:
 a third contact feature that electrically connects the source region of the first pull-up FINFET to a first power line;   a fourth contact feature that electrically connects the source regions of the first, second, and third pull-down FINFETs to a second power line;   a fifth contact feature that electrically connects the drain region of the first pass gate FINFET to a first bit line;   a sixth contact feature that electrically connects the drain region of the second pass gate FINFET to a second bit line;   a seventh contact feature that electrically connects the third gate electrode to a first word line;   an eighth contact feature that electrically connects the source region of the second pull-up FINFET to the first power line;   a ninth contact feature that electrically connects the source regions of the fourth, fifth, and sixth pull-down FINFETs to the second power line;   a tenth contact feature that electrically connects the drain region of the third pass gate FINFET to a third bit line;   an eleventh contact feature that electrically connects the drain region of the fourth pass gate FINFET to a fourth bit line; and   a twelfth contact feature that electrically connects the fourth gate electrode to a second word line.   
     
     
         14 . The SRAM cell of  claim 12 , further comprising:
 a third contact feature that electrically connects to the first contact feature and the second gate electrode, wherein the first and third contact features form an L-shape.   
     
     
         15 . The SRAM cell of  claim 14 , wherein the first and third contact features and the second gate electrode are in a same interconnect level of the SRAM cell. 
     
     
         16 . The SRAM cell of  claim 14 , further comprising:
 a fourth contact feature that electrically connects to the second contact feature and the first gate electrode, wherein the second and fourth contact features form an L-shape.   
     
     
         17 . The SRAM cell of  claim 16 , wherein the second and fourth contact features and the first gate electrode are in a same interconnect level of the SRAM cell. 
     
     
         18 . The SRAM cell of  claim 12 , further comprising:
 a first conductive feature that electrically connects to the source region of the second pass gate FINFET and the first gate electrode; and   a second conductive feature that electrically connects to the source region of the fourth pass gate FINFET and the second gate electrode.   
     
     
         19 . A dual port static random access memory (SRAM) cell including a plurality of fin field-effect transistors (FINFETs), the SRAM cell comprising:
 a first fin on a semiconductor substrate in an n-well region;   second, third, fourth, and fifth fins on the semiconductor substrate in a p-well region;   a sixth fin on the semiconductor substrate in the n-well region;   seventh, eighth, ninth, and tenth fins on the semiconductor substrate in a second p-well region,
 wherein the first and sixth fins include source, channel, and drain regions of first and second pull-up FINFETs, 
 wherein the second, third, and fourth fins include source, channel, and drain regions of first, second, and third pull-down FINFETs respectively, 
 wherein the third fin further includes source, channel, and drain regions of a first pass gate FINFET, 
 wherein the fifth fin includes source, channel, and drain regions of a second pass gate FINFETs, 
 wherein the seventh, eighth, and ninth fins include source, channel, and drain regions of fourth, fifth, and sixth pull-down FINFETs respectively, and the eighth fin further includes source, channel, and drain regions of a third pass gate FINFET, 
 wherein the tenth fin includes source, channel, and drain regions of a fourth pass gate FINFET; 
   a first gate electrode oriented in a first direction and over the channel regions of the first pull-up FINFET and the first, second, and third pull-down FINFETs;   a second gate electrode oriented in the first direction and over the channel regions of the second pull-up FINFET, and the fourth, fifth, and sixth pull-down FINFETs;   a first contact feature that electrically connects to at least the drain region of the first pull-up FINFET, the drain regions of the first, second, and third pull-down FINFETs, the source region of the first pass gate FINFET, and the second gate electrode; and   a second contact feature that electrically connects to at least the drain region of the second pull-up FINFET, the drain regions of the fourth, fifth, and sixth pull-down FINFETs, the source region of the third pass gate FINFET, and the first gate electrode.   
     
     
         20 . The SRAM cell of  claim 19 , further comprising a read port that includes at least two pull-down FINFETs in parallel and at least two pass gate FINFETs in parallel.