Co-integrated bulk acoustic wave resonators

Abstract

An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.

1 . An electrical circuit assembly, comprising:
 a semiconductor integrated circuit comprising one or more transistor structures; and   a first lateral-mode resonator fabricated upon a surface of a semiconductor integrated circuit, the first lateral-mode resonator comprising:   an acoustic energy storage layer;   a piezoelectric layer acoustically coupled to the acoustic energy storage layer; and   a first conductive region electrically coupled to the piezoelectric layer and electrically coupled to the semiconductor integrated circuit.   
     
     
         2 . The electrical circuit assembly of  claim 1 , comprising a first functionalized layer located upon the first lateral-mode resonator, the first functionalized layer configured to interact with a first species in proximity to the first lateral-mode resonator in a manner altering a mass of the first lateral-mode resonator in a presence of the first species. 
     
     
         3 . The electrical circuit assembly of  claim 2 , comprising an array of lateral-mode resonators;
 wherein the first lateral-mode resonator is included amongst other lateral-mode resonators comprising the array of lateral-mode resonators.   
     
     
         4 . The electrical circuit assembly of  claim 3 , wherein a second lateral-mode resonator included amongst the other lateral-mode resonators comprises different mechanical dimensions that the first lateral-mode resonator. 
     
     
         5 . The electrical circuit assembly of  claim 3 , wherein a second lateral-mode resonator included amongst the other lateral-mode resonators comprises a second functionalized layer, the second functionalized layer sensitized to a second species different from the first species. 
     
     
         6 . The electrical circuit assembly of  claim 1 , wherein the semiconductor integrated circuit and the first lateral-mode resonator form an oscillator circuit to provide frequency established at least in part by the first lateral-mode resonator. 
     
     
         7 . The electrical circuit assembly of  claim 1 , comprising an acoustic mirror located between the acoustic energy storage layer and the semiconductor integrated circuit. 
     
     
         8 . The electrical circuit assembly of  claim 1 , comprising:
 a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the acoustic energy storage layer and defining a cavity between the acoustic energy storage layer and the semiconductor integrated circuit;   wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region.   
     
     
         9 . The electrical circuit assembly of  claim 8 , wherein the dielectric region is mechanically coupled to the acoustic energy storage, layer using multiple, tether structures. 
     
     
         10 . The electrical circuit assembly of  claim 9 , wherein the multiple tether structures comprise respective tether structures located in respective regions along the first lateral-mode resonator corresponding to respective nodes where mechanical displacement of a suspended portion of the first lateral-mode resonator is suppressed or inhibited when a suspended portion of the first lateral-mode resonator resonates according to a lateral acoustic mode. 
     
     
         11 . The electrical circuit assembly of  claim 1 , where the first lateral-mode resonator is housed in an evacuated enclosure. 
     
     
         12 . The electronic circuit assembly of  claim 1 , wherein the acoustic energy storage layer comprises a semiconductor material. 
     
     
         13 . A method for fabricating an electrical circuit assembly, comprising:
 forming a first lateral-mode resonator upon a semiconductor integrated circuit, the semiconductor integrated circuit comprising one or more transistor structures, the forming the first lateral-mode resonator comprising:   forming an acoustic energy storage layer;   forming a piezoelectric layer acoustically coupled to the acoustic energy storage layer;   forming a conductive region electrically coupled to piezoelectric layer and electrically coupled to the semiconductor integrator circuit; and   functionalizing a portion of the first lateral-mode resonator including forming a first functionalized layer configured to interact with a first species in proximity to the first lateral-mode resonator in a manner altering a mass of the lateral-mode resonator in the presence of the first species.   
     
     
         14 . The method of  claim 13 , comprising forming an array of lateral-mode resonators;
 wherein the first lateral-mode resonator is included amongst other lateral-mode resonators comprising the array of lateral-mode resonators.   
     
     
         15 . The method of  claim 13 , wherein a second lateral-mode resonator included amongst the other lateral-mode resonators comprises a second functionalized layer, the second functionalized layer sensitized to a second species different from the first species. 
     
     
         16 . The method of  claim 13 , comprising forming a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the acoustic energy storage layer and defining a cavity between the acoustic energy storage layer and the semiconductor integrated circuit;
 wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region.   
     
     
         17 . The method of  claim 16 , wherein the dielectric region is mechanically coupled to the acoustic energy storage layer using multiple tether structures. 
     
     
         18 . The method of  claim 13 , wherein the multiple tether structures comprise respective tether structures located in respective regions along the first lateral-mode resonator corresponding to respective nodes where mechanical displacement of a suspended portion of the resonator is suppressed or inhibited when a suspended portion of the first lateral-mode resonator resonates according to a lateral acoustic mode. 
     
     
         19 . The method of  claim 13 , wherein the acoustic energy storage layer is formed without disrupting operating characteristics of the one or more transistor structures comprising the semiconductor integrated circuit. 
     
     
         20 . An electrical circuit assembly, comprising:
 a semiconductor integrated circuit comprising one or more transistor structures; and   a first lateral-mode resonator fabricated upon a surface of a semiconductor integrated circuit, the first lateral-mode resonator comprising:
 an acoustic energy storage layer; 
 a piezoelectric layer acoustically coupled to the acoustic energy storage layer; and 
 a first conductive region electrically coupled to the piezoelectric layer and electrically coupled to the semiconductor integrated circuit; and 
   a dielectric region located upon a surface of the semiconductor integrated circuit,   the dielectric region coupled to the acoustic energy storage layer and defining a cavity between the acoustic energy storage layer and the semiconductor integrated circuit;   wherein the acoustic energy storage layer includes a released configuration suspended from h dielectric region;   wherein the dielectric region is mechanically coupled to the acoustic energy storage layer using multiple tether structures, the multiple tether structures comprising respective tether structures located in respective regions along the first lateral-mode resonator corresponding to respective nodes where mechanical displacement of a suspended portion of the resonator is suppressed or inhibited when a suspended portion of the first lateral-mode resonator resonates according to a lateral acoustic mode; and   wherein the semiconductor integrated circuit and the first lateral-mode resonator form an oscillator circuit to provide an oscillation frequency established at least in part by the first lateral-mode resonator.