Four terminal stacked complementary junction field effect transistors

Abstract

A semiconductor device that is composed of an epitaxial semiconductor material stacked structure that includes a first epitaxial channel for a first junction field effect transistor (JFET) atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor (JFET). A commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region. A channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate. An epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and the second epitaxial channel region.

1 . A semiconductor device comprising:
 an epitaxial semiconductor material stacked structure comprising a first epitaxial channel for a first junction field effect transistor (JFET) region atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor, wherein a commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region, wherein a channel length for each of the first and second JFET is substantially perpendicular to an upper surface of the supporting substrate; and   an epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and said second epitaxial channel region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a width of the epitaxial semiconductor material stack structure is entirely uniform extending from the second epitaxial channel region portion of the second JFET to the first epitaxial channel region portion of the first JFET across the interface including the commonly electrically contacted source/drain region for each of the first JFET and the second JFET. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a first source/drain region for the first JFET provided by a doped semiconductor layer that is present atop an isolation structure of the supporting substrate. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a second source/drain region for the second JFET provided by a doped semiconductor epitaxial semiconductor material that is formed on an end of the second epitaxial channel region opposite an end of the channel region that the commonly electrically contacted source/drain region for the second JFET is present. 
     
     
         5 . The semiconductor device of  claim 1 , wherein sidewalls for the first epitaxial channel region are aligned with sidewalls of the commonly electrically contacted source/drain region for each of the first JFET and the second JFET, and the sidewalls of the commonly electrically contacted source/drain region for each of the first JFET and the second JFET are aligned to sidewalls for the second epitaxial channel region. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the commonly electrically contacted source/drain region for each of the first JFET and the second JFET includes a first conductivity type source/drain region that is in direct contact with the first epitaxial channel region and a second conductivity type source/drain region that is in direct contact with the second epitaxial channel region, the first conductivity type source/drain region being in direct contact with the second conductivity source/drain region. 
     
     
         7 . A semiconductor device comprising:
 an epitaxial semiconductor material stacked structure comprising a first epitaxial channel for a first four terminal junction field effect transistor (JFET) region atop a supporting substrate and a second epitaxial channel region for a second four terminal junction field effect transistor, wherein a commonly electrically contacted source/drain region for each of the first four terminal JFET and the second four terminal JFET is positioned at an interface of the first and second epitaxial channel region and provides the output node for each of the first and second four terminal JFETs, wherein a channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate; and   an epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and said second epitaxial channel region.   
     
     
         8 . The semiconductor device of  claim 7 , wherein a width of the epitaxial semiconductor material stack structure is entirely uniform extending from the second epitaxial channel region portion of the second JFET to the first epitaxial channel region portion of the first JFET across the interface including the commonly electrically contacted source/drain region for each of the first JFET and the second JFET. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the first four terminal junction field effect transistor is an n-type JFET having a source region connected to ground, a drain region being said commonly electrically contacted source/drain region for the first four terminal JFET connected to the output node, a first sidewall of the gate structure to the first four terminal junction field effect transistor connected to a first input node and a second sidewall of the gate structure to a second input node. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the source region of the n-type JFET is connected to a lower power supply (VSS). 
     
     
         11 . The semiconductor device of  claim 9 , wherein the second four terminal junction field effect transistor is a p-type JFET having a source region connected to a power supply (Vdd), a drain region being said commonly electrically contacted source/drain region for the first four terminal JFET connected to the output node, a first sidewall of the gate structure to the first four terminal junction field effect transistor connected to a first input and a second sidewall of the gate structure to a second input.