Liquid crystal display panel

Abstract

Disclosed is a liquid crystal display panel. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

What is claimed is: 
     
         1 . A liquid crystal display panel, comprising a thin-film transistor, wherein:
 an active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers; and   the active layer is in contact with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.   
     
     
         2 . The panel according to  claim 1 , wherein the active layer comprises three film layers. 
     
     
         3 . The panel according to  claim 1 , wherein a second film layer is formed between a first film layer and a third film layer, wherein:
 the first film layer is a low-speed deposited film layer, and the third film layer is a high-speed deposited film layer, and   a speed of forming the second film layer is between a speed of forming the first film layer and a speed of forming the third film layer.   
     
     
         4 . The panel according to  claim 3 , wherein the active layer is in contact with the passivation layer on the second film layer of the active layer. 
     
     
         5 . The panel according to  claim 3 , wherein a sum of thicknesses of the first film layer and the second film layer accounts for ⅓ of a thickness of the entire active layer. 
     
     
         6 . The panel according to  claim 4 , wherein a sum of thicknesses of the first film layer and the second film layer accounts for ⅓ of a thickness of the entire active layer. 
     
     
         7 . The panel according to  claim 1 , further comprising a substrate, a gate formed on the substrate, and a gate insulation layer formed on the gate; wherein the active layer is formed on the gate insulation layer. 
     
     
         8 . The panel according to  claim 3 , wherein an ohmic contact layer is formed on the high-speed deposited film layer. 
     
     
         9 . The panel according to  claim 8 , wherein the source and the chain of the thin-film transistor are formed on the ohmic contact layer. 
     
     
         10 . The panel according to  claim 9 , wherein the passivation layer is formed on the source and the drain of the thin-film transistor.