Wafer scale testing and initialization of small die chips

Abstract

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

What is claimed is: 
     
         1 . A chip intermediate body, comprising:
 a super-die separated from a wafer, the super-die including a plurality of small-dies, the small-dies respectively being cut out as semiconductor chips;   a cut region provided along edges of the small-dies, the cut region being cut to separate the semiconductor chips;   a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted on a plurality of test pads by a probe of a test unit to test the small-dies; and   electric wiring provided continuously with the cut region to connect the small-dies of the super-die and the contact region.   
     
     
         2 . The chip intermediate body of  claim 1 , wherein each of the small-dies includes bumps on a surface of the small-dies. 
     
     
         3 . The chip intermediate body of  claim 2 , wherein
 the test pads are configured to be contacted by respective contact points of the probe of the test unit, and   each of the test pads has a larger area than each of the bumps.   
     
     
         4 . The chip intermediate body of  claim 1 , wherein the cut region includes other electric wiring that at least interconnects the small-dies and connects the small-dies and the contact region. 
     
     
         5 . The chip intermediate body of  claim 4 , wherein the other electric wiring is electrically connected with the electric wiring. 
     
     
         6 . The chip intermediate body of  claim 4 , wherein each of the small-dies includes circuit wiring, and
 the other electric wiring and the circuit wiring are present in the same layer of the chip intermediate body.   
     
     
         7 . The chip intermediate body of  claim 6 , wherein the circuit wiring is set apart from a boundary between the small-dies and the cut region. 
     
     
         8 . The chip intermediate body of  claim 1 , wherein the chip intermediate body is a plate member and has a generally square shape in a plane view. 
     
     
         9 . The chip intermediate body of  claim 8 , wherein the contact region is provided along edges of the chip intermediate body. 
     
     
         10 . A chip intermediate body manufacturing system for manufacturing a chip intermediate body, the chip intermediate body comprising:
 a super-die separated from a wafer, the super-die including a plurality of small-dies, the small-dies respectively being separated as semiconductor chips;   a cut region provided along edges of the small-dies, the cut region being cut to cut out the semiconductor chips;   a contact region provided opposite to the small-dies across the cut region, the contact region being configured to be contacted on a plurality of test pads by a probe of a test unit to test the small-dies; and   electric wiring provided continuously with the cut region to connect the small-dies of the super-die and the contact region.   
     
     
         11 . The chip intermediate body of  claim 10 , wherein each of the small-dies includes bumps on a surface of the small-dies. 
     
     
         12 . The chip intermediate body of  claim 11 , wherein
 the test pads are configured to be contacted by respective contact points of the probe of the test unit, and   each of the test pads has a larger area than each of the bumps.   
     
     
         13 . The chip intermediate body of  claim 10 , wherein the cut region includes other electric wiring that at least interconnects the small-dies and connects the small-dies and the contact region. 
     
     
         14 . The chip intermediate body of  claim 13 , wherein the other electric wiring is electrically connected with the electric wiring. 
     
     
         15 . The chip intermediate body of  claim 13 , wherein each of the small-dies includes circuit wiring, and
 the other electric wiring and the circuit wiring are present in the same layer of the chip intermediate body.   
     
     
         16 . The chip intermediate body of  claim 15 , wherein the circuit wiring is set apart from a boundary between the small-dies and the cut region. 
     
     
         17 . The chip intermediate body of  claim 10 , wherein the chip intermediate body is a plate member and has a generally square shape in a plane view. 
     
     
         18 . The chip intermediate body of  claim 17 , wherein the contact region is provided along edges of the chip intermediate body. 
     
     
         19 . A semiconductor chip manufacturing system, comprising:
 a fabrication unit for fabricating a chip intermediate body including a super-die separated from a wafer, the super-die including a cut region, a contact region, electric wiring, and a plurality of small-dies, the small dies being separated as semiconductor chips, the cut region being provided along edges of the small-dies, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the small-dies across the cut region, the electric wiring being provided continuously with the cut region to connect the small-dies of the super-die and the contact region;   a test unit for testing the small-dies, the test unit including a probe to contact the contact region to test the small-dies; and   a separation unit for cutting the cut region to separate the semiconductor chips.   
     
     
         20 . A method for testing a chip area comprising:
 fabricating a chip intermediate body including a super-die, the super-die including a cut region, a contact region, electric wiring, and a plurality of small-dies, the small-dies being separated as semiconductor chips, the cut region being provided along edges of the small-dies, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the small-dies across the cut region, the electric wiring being provided continuously with the cut region to connect the small-dies of the super-die and the contact region; and   testing the small-dies with a probe of a test unit contacting the contact region.