Power device and method for fabricating the same

Abstract

A power device having fast switching characteristic, while keeping EMI noise to a minimum and a method of fabricating the same are provided. The power device includes a first field stop layer having a first conductivity type, a first drift region formed on the first field stop layer and having a first conductivity type in an impurity concentration that is lower than the first field stop layer, a buried region formed on the first drift region and having the first conductivity type in an impurity concentration that is higher than the first drift region, a second drift region formed on the buried region, a power device cell formed at an upper portion of the second drift region, and a collector region formed below the first field stop layer.

What is claimed is: 
     
         1 . A method, comprising:
 forming a field stop layer having a first conductivity type;   forming a first drift region disposed on the field stop layer and having the first conductivity type in an impurity concentration that is lower than the field stop layer;   forming a buried region disposed on the first drift region and having the first conductivity type in an impurity concentration that is higher than the first drift region;   forming a second drift region disposed on the buried region;   forming a power device cell disposed at an upper portion of the second drift region; and   forming a collector region disposed below the field stop layer.   
     
     
         2 . The method of  claim 1 , wherein the field stop layer is a first field stop layer,
 the method further comprising forming a second field stop layer disposed between the first field stop layer and the first drift region, the second field stop layer having the first conductivity type with an impurity concentration portion that is higher than the first field stop layer.   
     
     
         3 . The method of  claim 2 , wherein the second field stop layer has a higher impurity concentration than the buried region. 
     
     
         4 . The method of  claim 2 , wherein the first drift region is formed by an epitaxial growth on the second field stop layer. 
     
     
         5 . The method of  claim 2 , wherein the second field stop layer is formed by an ion implantation process so that the impurity concentration is higher than the first field stop layer. 
     
     
         6 . The method of  claim 2 , wherein the second field stop layer includes, on a same level, a first region having a first impurity concentration, and a second region having a second impurity concentration which is higher than the first impurity concentration. 
     
     
         7 . The method of  claim 1 , wherein the second drift region has the first conductivity type in an impurity concentration that is lower than the buried region, and
 the first drift region and the second drift region each has a constant impurity concentration profile in a depth direction.   
     
     
         8 . The method of  claim 1 , wherein the second drift region includes a first conductivity type pillar and a second conductivity type pillar, each of which are formed by extending on the buried region in a perpendicular direction and in alternate arrangement in a horizontal direction, and
 the first conductivity type pillar has a lower impurity concentration than the buried region.   
     
     
         9 . The method of  claim 1 , wherein the buried region comprises a first region having an increasing impurity concentration from the first drift region, and a second region adjacent to the first region and having a decreasing impurity concentration to the second drift region. 
     
     
         10 . The method of  claim 1 , further comprising:
 forming a base region disposed at an upper portion of the second drift region and having a second conductivity type which is different from the first conductivity type;   forming an emitter region disposed on a surface portion within the base region and having the first conductivity type; and   forming a gate electrode formed by interposing a gate insulating layer on the second drift region, the base region and the emitter region.   
     
     
         11 . A method for fabricating a power device, comprising:
 preparing a semiconductor substrate having a first conductivity type;   forming a first drift region by epitaxial growth on a front surface of the semiconductor substrate to provide an impurity concentration of the first conductivity type that is lower than the semiconductor substrate;   forming a buried region by ion-implanting impurity ions having the first conductivity type on a front surface of the first drift region;   forming a second drift region on the buried region;   forming a power device cell at an upper portion of the second drift region;   forming a field stop layer by grinding a back surface which is opposite to the front surface of the semiconductor substrate; and   forming a collector region at a lower portion of the field stop layer.   
     
     
         12 . The method of  claim 11 , wherein the forming the second drift region comprises epitaxial growing on a front surface of the buried region to provide the impurity concentration of the first conductivity type that is lower than the semiconductor substrate. 
     
     
         13 . The method of  claim 12 , wherein the second drift region is formed to have the first conductivity type in the impurity concentration that is lower than the buried region, and
 the first and second drift regions each have a constant impurity concentration profile in a depth direction.   
     
     
         14 . The method of  claim 12 , wherein the forming the second drift region includes epitaxial growing to provide the impurity concentration of the first conductivity type that is substantially same as the first drift region. 
     
     
         15 . The method of  claim 14 , wherein the buried region is formed such that the impurity concentration increases from the first drift region to reach a maximum impurity concentration, and then decreases to the second drift region. 
     
     
         16 . The method of  claim 15 , wherein impurity concentration profile of the buried region is formed such that a symmetry is formed between the first drift region and the second drift region. 
     
     
         17 . The method of  claim 11 , wherein the field stop layer is a first field stop layer,
 the method further comprising prior to forming the first drift region, forming a second field stop layer having a higher impurity concentration portion than the semiconductor substrate, by ion-implanting impurity ions having the first conductivity type on the front surface of the semiconductor substrate.   
     
     
         18 . The method of  claim 17 , wherein the second field stop layer has a higher impurity concentration than the buried region. 
     
     
         19 . The method of  claim 17 , wherein the forming the second field stop layer comprises:
 first ion implantation of forming an implanted layer by ion-implanting impurity ions having the first conductivity type on the front surface of the semiconductor substrate; and   second ion implantation of ion-implanting impurity ions having the first conductivity type into a portion of the implanted layer so that the impurity concentration of the portion of the implanted layer is higher than the impurity concentration of a rest portion of the implanted layer.   
     
     
         20 . The method of  claim 11 , wherein the forming the power device cell comprises:
 forming a base region having a second conductivity type different from the first conductivity type on a predetermined area of a surface of the second drift region;   forming an emitter region having the first conductivity type on a predetermined area of a surface of the base region;   forming a gate electrode by interposing a gate insulating layer on the second drift region, the base region and the emitter region; and   forming an emitter electrode on the base region and the emitter region.   
     
     
         21 . The method of  claim 11 , wherein the forming the power device cell comprises:
 forming a base region having a second conductivity type different from the first conductivity type on a predetermined area of a surface of the second drift region;   forming an emitter region having the first conductivity type on a predetermined area of a surface of the base region;   forming a trench having a receiving space therein adjacent to one side surface of the base region and the emitter region, by digging from a surface of the second drift region to a predetermined depth;   forming a gate insulating layer for covering an inner surface of the trench;   forming a gate electrode within the trench which has the gate insulating layer formed therein; and   forming an emitter electrode on the base region and the emitter region.   
     
     
         22 . The method of  claim 11 , wherein the forming the collector region further comprising:
 ion-implanting impurity ions having a second conductivity type different from the first conductivity type in a lower portion of the field stop layer.