Isolation device

Abstract

In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . An isolation capacitor, comprising:
 a first capacitive element in electrical communication with a first circuit and having a first area;   a second capacitive element in electrical communication with a second circuit that operates at a different voltage than the first circuit, wherein the second capacitive element comprises a second area that is different from the first area; and   at least one isolation layer positioned between the first capacitive element and the second capacitive element such that i) a first isolation boundary of the at least one isolation layer extends beyond a first end of the second capacitive element, and ii) a second isolation boundary of the at least one isolation layer substantially overlaps with at least a portion of a second end of the second capacitive element that is opposite the first end of the second capacitive element,   wherein the at least one isolation layer substantially prohibits electrical current from flowing between the first capacitive element and the second capacitive element, thereby maintaining an electrical isolation between the first circuit and second circuit, and wherein the at least one isolation layer allows a capacitively coupled signal to travel between the first capacitive element and the second capacitive element thereby enabling communication between the first circuit and second circuit even though the first circuit and second circuit are electrically isolated from one another.   
     
     
         22 . The isolation capacitor of  claim 21 , wherein the first area of the first capacitive element is smaller than the second area of the second capacitive element. 
     
     
         23 . The isolation capacitor of  claim 22 , wherein the first area of the first capacitive element dictates a capacitance between the first capacitive element and the second capacitive element. 
     
     
         24 . The isolation capacitor of  claim 22 , wherein a center of the first area is offset from a center of the second area. 
     
     
         25 . The isolation capacitor of  claim 22 , wherein at least one of the first area and second area are at least one of circular and elliptical. 
     
     
         26 . The isolation capacitor of  claim 21 , wherein the first isolation boundary is defined by an interface between the at least one isolation layer and an edge of at least one first wiring layer, and wherein the second isolation boundary is defined by an interface between the at least one isolation layer and a location near an edge of at least one second wiring layer. 
     
     
         27 . The isolation capacitor of  claim 21 , wherein the first capacitive element and the second capacitive element comprise metal plates. 
     
     
         28 . The isolation capacitor of  claim 21 , wherein the second capacitive element comprises a conductive layer having at least a portion that is outside of the second isolation boundary, the conductive layer being in communication with the second circuit. 
     
     
         29 . The isolation capacitor of  claim 21 , wherein the first circuit operates at a voltage that is at least 2 kV larger than a voltage at which the second circuit operates. 
     
     
         30 . The isolation capacitor of  claim 21 , wherein the second capacitive element is separated from a substrate by a portion of the at least one isolation layer. 
     
     
         31 . The isolation capacitor of  claim 30 , wherein the at least one isolation layer includes one or more wiring layers outside of the first and second isolation boundaries. 
     
     
         32 . The isolation capacitor of  claim 31 , wherein a surface of the second capacitive element and a surface of a first wiring layer of the one or more wiring layers are coplanar. 
     
     
         33 . An isolation system, comprising:
 a first circuit operating at a first voltage range;   a second circuit operating at a second voltage range that is different from the first voltage range; and   a capacitive isolator that electrically isolates the first circuit from the second circuit while also enabling control signals to pass between the first circuit and second circuit in the form of electrical flux, wherein the capacitive isolator comprises:
 a first capacitive element in electrical communication with the first circuit; 
 a second capacitive element on a substrate, the second capacitive element being positioned in an overlapping arrangement with the first capacitive element and being in electrical communication with the second circuit; and 
 an isolation layer positioned between the first capacitive element and the second capacitive element such that i) a first isolation boundary of the isolation layer extends beyond a first end of the second capacitive element, and ii) a second isolation boundary of the isolation layer overlaps with at least a portion of a second end of the second capacitive element that is opposite the first end, wherein the isolation layer substantially prevents current from flowing directly between the first capacitive element and the second capacitive element, but enables the electrical flux to pass between the first capacitive element and the second capacitive element. 
   
     
     
         34 . The isolation system of  claim 33 , wherein the first isolation boundary is defined by an interface between the isolation layer and an edge of at least one first wiring layer, and wherein the second isolation boundary is defined by an interface between the isolation layer and a location near an edge of at least one second wiring layer. 
     
     
         35 . The isolation system of  claim 34 , wherein the substrate comprises a silicon integrated circuit chip. 
     
     
         36 . The isolation system of  claim 35 , wherein the at least one isolation layer further comprises one or more wiring layers, and wherein a first wiring layer of the one or more wiring layers has a surface that is coplanar with a surface of the second capacitive element. 
     
     
         37 . The isolation system of  claim 34 , wherein an area of the first capacitive element is different from an area of the second capacitive element. 
     
     
         38 . The isolation system of  claim 37 , wherein a center of the first capacitive element is positioned offset from a center of the second capacitive element. 
     
     
         39 . A method of operating a capacitive isolator, comprising:
 receiving electrical current at a first capacitive element having a first area, wherein the first electrical current is received from a first circuit operating at a first voltage range;   converting the first electrical current into electric flux at the first capacitive element;   transmitting the electric flux across an isolation layer that electrically isolates the first capacitive element from a second capacitive element and thereby electrically isolates the first circuit from a second circuit operating at a second voltage range that is different from the first voltage range;   receiving the electric flux at the second capacitive element, wherein the second capacitive element comprises a second area that is larger than the first area of the first capacitive element; and   converting the electric flux received at the second capacitive element into second current that is provided to the second circuit,   wherein i) a first isolation boundary of the isolation layer extends beyond a first end of the second capacitive element, and ii) a second isolation boundary of the isolation layer overlaps with at least a portion of a second end of the second capacitive element that is opposite the first end.   
     
     
         40 . The method of  claim 39 , wherein the first isolation boundary is defined by an interface between the isolation layer and a first metal layer, and wherein the second isolation boundary is defined by an interface between the isolation layer and a location near a second metal layer.