Devices related to barrier for metallization of gallium based semiconductor

Abstract

Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.

1 . (canceled) 
     
     
         2 . A method of fabricating heterojunction bipolar transistors, the method comprising:
 forming a collector that includes gallium arsenide; and   forming a capacitor structure over the collector, the capacitor structure including an emitter that includes indium gallium phosphide and a ledge, a metal layer over the emitter, and a tantalum nitride layer configured to separate and function as a barrier between the metal layer and the emitter, and the collector layer and the emitter being included in a heterojunction bipolar transistor;   measuring a capacitance of the capacitor structure, the capacitance being representative of a thickness of the emitter; and   performing process control for a fabrication process for heterojunction bipolar transistors based on the measured capacitance of the capacitance structure.   
     
     
         3 . The method of  claim 2  wherein the performing process control includes adjusting a process parameter. 
     
     
         4 . The method of  claim 3  further comprising calculating the emitter thickness based on the measured capacitance, the adjusting the process parameter being in response to the calculated emitter thickness being outside of a range of emitter thickness. 
     
     
         5 . The method of  claim 3  wherein the process parameter is associated with adjusting an emitter deposition technique to obtain a more uniform distribution of emitter thicknesses across a wafer. 
     
     
         6 . The method of  claim 3  wherein the process parameter is associated with fixing a systematic problem. 
     
     
         7 . The method of  claim 2  wherein the performing process control includes verifying that a thickness of the emitter is within a range of emitter thickness. 
     
     
         8 . The method of  claim 2  wherein the fabricating the capacitor structure includes forming a base of the heterojunction bipolar transistor over the collector, the base being between the collector and the emitter. 
     
     
         9 . The method of  claim 8  wherein the base includes p-type gallium arsenide and the collector includes n-type gallium arsenide. 
     
     
         10 . The method of  claim 8  further comprising forming a second metal layer disposed over and in electrical communication with the base, the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer. 
     
     
         11 . The method of  claim 2  wherein the fabricating the capacitor structure is performed such that at least a portion of the collector layer and at least a portion of the emitter are within a footprint of the tantalum nitride layer. 
     
     
         12 . The method of  claim 2  wherein a capacitance density of the capacitor structure is at least 2.0 femtofarads per square micrometer. 
     
     
         13 . A system for monitoring a heterojunction bipolar transistor fabrication process, the system comprising:
 a process assembly configured to form an indium gallium phosphide emitter layer including a ledge and being over a base layer, a tantalum nitride layer over the indium gallium phosphide emitter layer, and a metal layer over the tantalum nitride layer, the base layer and the indium gallium phosphide emitter layer being included in a heterojunction bipolar transistor;   a monitoring assembly configured to measure capacitance between the metal layer and the base layer, the measured capacitance being representative of a thickness of the indium gallium phosphide emitter layer; and   a process control assembly configured to perform process control based on the measured capacitance.   
     
     
         14 . The system of  claim 13  wherein the process control assembly is configured to perform process control by at least adjusting a process parameter. 
     
     
         15 . The system of  claim 14  wherein the adjusted process parameter causes the process assembly to form indium gallium phosphide emitter layers with thicknesses within a desired range. 
     
     
         16 . The system of  claim 13  wherein the process control assembly is configured to perform process control by at least verifying that the thickness of the indium gallium phosphide emitter layer is within a desired range. 
     
     
         17 . The system of  claim 13  wherein the process assembly is configured to form a collector layer of the heterojunction bipolar transistor, the collector layer including gallium arsenide, and the base layer being positioned between the collector layer and the indium gallium phosphide emitter layer. 
     
     
         18 . A method of fabricating a heterojunction bipolar transistor, the method comprising:
 forming a collector over a gallium arsenide substrate, the collector layer including gallium arsenide; and   forming a base over the collector;   forming an emitter over the base, the emitter including indium gallium phosphide and a ledge; the collector, the base, and the emitter being included in a heterojunction bipolar transistor;   forming a tantalum nitride layer over the emitter such that at least a portion of the collector and at least a portion of the emitter are within a footprint of the tantalum nitride layer; and   forming a metal layer over the tantalum nitride layer, the tantalum nitride layer configured to separate and function as a barrier between the metal layer and the emitter.   
     
     
         19 . The method of  claim 18  further comprising forming a second metal layer disposed over and in electrical communication with the base, the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer. 
     
     
         20 . The method of  claim 18  wherein the heterojunction bipolar transistor is fabricated such that the emitter includes a surface in physical contact with the tantalum nitride layer and a passivation structure. 
     
     
         21 . The method of  claim 18  further comprising:
 measuring a capacitance between the metal layer and the base, the capacitance being representative of a thickness of the emitter; and 
 adjusting a process parameter based on the measured capacitance.