Instruction And Logic For In-Order Handling In An Out-Of-Order Processor

Abstract

In one embodiment, a processor includes a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued instructions of a program. The at least one execution logic is to execute at least some instructions of the program out-of-order, and the decode logic is to decode and provide a first in-order memory instruction of the program to the issue logic. In turn, the issue logic is to order the first in-order memory instruction ahead of a second in-order memory instruction of the program. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a core comprising an out-of-order pipeline including a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued instructions of a program, wherein the at least one execution logic is to execute at least some instructions of the program out-of-order, the decode logic to decode a first in-order memory instruction of the program and provide the decoded first in-order memory instruction to the issue logic, the issue logic to order the first in-order memory instruction ahead of a second in-order memory instruction of the program, the first in-order memory instruction an unordered memory instruction in a source version of the program, wherein a compiler logic is to generate the first in-order memory instruction from an unordered memory instruction of the program, based at least in part on an identifier associated with at least one operand of the unordered memory instruction.   
     
     
         2 . The processor of  claim 1 , wherein the issue logic is to issue the first in-order memory instruction to the at least one execution logic with a higher priority than the second in-order memory instruction by association of a priority indicator with the first in-order memory instruction. 
     
     
         3 . The processor of  claim 1 , wherein the compiler logic is to generate the first in-order memory instruction having a different machine code than a machine code for the unordered memory instruction. 
     
     
         4 . The processor of  claim 1 , wherein the issue logic comprises:
 a first storage to store pending in-order memory instructions; and   a second storage to store pending unordered instructions.   
     
     
         5 . The processor of  claim 4 , wherein the decode logic is to provide the first in-order memory instruction to the first storage of the issue logic, the first storage comprising a first-in-first-out queue. 
     
     
         6 . The processor of  claim 5 , wherein the issue logic, in response to a determination that another in-order memory instruction of the program is in flight in the processor, is to issue an unordered instruction of the program to the at least one execution logic. 
     
     
         7 . The processor of  claim 5 , wherein the issue logic, in response to a first determination that another in-order memory instruction of the program is not in flight in the processor and a second determination that one or more prior in-order memory instructions of the program have been executed, is to issue the first in-order memory instruction to the at least one execution logic. 
     
     
         8 . The processor of  claim 7 , wherein the issue logic, in response to a determination that the another in-order memory instruction of the program is in flight in the processor, is to not issue the first in-order memory instruction to the at least one execution logic and issue at least one unordered instruction of the program to the at least one execution logic. 
     
     
         9 . The processor of  claim 1 , wherein the issue logic, in response to a determination that the first in-order memory instruction is in a ready queue but not ready to issue, is to issue at least one unordered instruction of the program to the at least one execution logic. 
     
     
         10 . The processor of  claim 1 , wherein the issue logic is to issue one or more unordered instructions of the program to the at least one execution logic unordered with respect to the first in-order memory instruction. 
     
     
         11 . The processor of  claim 1 , wherein the first in-order memory instruction comprises a user-level instruction of an instruction set architecture to specify in-order execution. 
     
     
         12 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
 identifying a first variable having a directive indicator to indicate in-order handling;   identifying an operand of a load/store instruction of a code block associated with the first variable;   translating the load/store instruction to an in-order load/store instruction encoded by a first machine code, to enable execution of the first machine code by an execution logic of a processor; and   storing the first machine code in a destination storage.   
     
     
         13 . The machine-readable medium of  claim 12 , wherein the method further comprises translating a second load/store instruction to an unordered load/store instruction encoded by a second machine code, the second load/store instruction not having an operand associated with a variable marked with a directive indicator. 
     
     
         14 . The machine-readable medium of  claim 12 , wherein the method further comprises ordering the in-order load/store instruction ahead of a second in-order load/store instruction associated with the operand, the second in-order load/store instruction succeeding the load/store instruction in program order. 
     
     
         15 . The machine-readable medium of  claim 14 , wherein the method further comprises ordering one or more unordered load/store instructions ahead of the in-order load/store instruction. 
     
     
         16 . The machine-readable medium of  claim 12 , wherein the method further comprises ordering a third in-order load/store instruction of the code block ahead of the in-order load/store instruction, the third in-order load/store instruction succeeding the in-order load/store instruction in program order and associated with a different operand than the operand of the in-order load/store instruction. 
     
     
         17 . A system comprising:
 a processor including a first core having:
 a decode logic to decode instructions; 
 an issue logic to issue decoded instructions, the issue logic associated with a first queue to store in-order memory access instructions and a second storage to store unordered instructions; and 
 a first execution logic to execute issued instructions of a program, wherein the issue logic is to store a decoded first in-order memory access instruction of the program and a decoded second in-order memory access instruction of the program in the first queue and store one or more unordered instructions of the program in the second storage, wherein a compiler logic is to generate the first in-order memory access instruction from an unordered memory access instruction, based at least in part on an identifier associated with at least one operand of the unordered memory access instruction; and 
   a dynamic random access memory coupled to the processor.   
     
     
         18 . The system of  claim 17 , wherein the issue logic is to provide the decoded first in-order memory access instruction to the first execution logic ahead of the decoded second in-order memory access instruction of the program and unordered with respect to one or more of the one or more unordered instructions. 
     
     
         19 . The system of  claim 18 , wherein the issue logic is to issue the decoded first in-order memory access instruction to the first execution logic with a higher priority than the decoded second in-order memory access instruction by association of a priority indicator with the decoded first in-order memory access instruction. 
     
     
         20 . The system of  claim 17 , wherein the at least one operand comprises a memory-mapped input/output location to be accessed during the program, the program comprising a device driver for an embedded controller, wherein the first core comprises an out-of-order pipeline.