Vertical memory device

Abstract

A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

What is claimed is: 
     
         1 . A vertical memory device comprising:
 a substrate having a cell array region and a connection region adjacent to the cell array region;   a plurality of gate electrode layers stacked on the substrate in a vertical direction, the plurality of gate electrode layers including a first group of gate electrode layers which extends in a first horizontal direction from the cell array region to the connection region, each of the first group of gate electrode layers being spaced apart from each other by an insulating layer; and   a plurality of channel columns passing through the plurality of gate electrode layers in the vertical direction on the cell array region,   wherein the first group of gate electrode layers includes:
 a first gate electrode layer on the substrate; 
 a second gate electrode layer stacked on the first gate electrode layer and covering only a portion of the first gate electrode layer at the connection region, thereby exposing a first pad region on the first gate electrode layer; 
 a third gate electrode layer stacked on the second gate electrode layer and covering only a portion of the second gate electrode layer at the connection region, thereby exposing a second pad region on the second gate electrode layer; and 
 a fourth gate electrode layer stacked on the third gate electrode layer and covering only a portion of the third gate electrode layer on the connection region, thereby exposing a third pad region on the third gate electrode layer and a fourth pad region on the fourth gate electrode layer respectively, 
   wherein each of the first group of gate electrode layers extends as long as a first distance from the cell array region to the connection region, thereby the first group of gate electrode layers form an aligned edges on the connection region,   wherein a height of the plurality of gate electrode layers on the cell array region is greater than 3.5 μm and less than 10 μm in the vertical direction,   wherein a number of the plurality of gate electrode layers is equal to or greater than sixty, and   wherein the vertical memory device further includes first to fourth contact plugs formed vertically on the first to fourth pad regions respectively.   
     
     
         2 . The vertical memory device of  claim 1 , wherein the first to fourth contact plugs are aligned in a second horizontal direction which is perpendicular to the first horizontal direction. 
     
     
         3 . The vertical memory device of  claim 2 , wherein the number of the plurality of gate electrode layers is smaller than two hundreds. 
     
     
         4 . The vertical memory device of  claim 3 , wherein the first to fourth gate electrode layers combined together form a first stepped structure in the second horizontal direction. 
     
     
         5 . The vertical memory device of  claim 4 , wherein the first pad region locates lower than the second pad region, the second pad region locates lower than the third pad region, and the third pad region locates lower than the fourth pad region respectively. 
     
     
         6 . The vertical memory device of  claim 5 , wherein the plurality of gate electrode layers further include a second group of gate electrode layers stacked on the substrate and horizontally extending as long as a second distance from the cell array region to the connection region, the second distance is different from the first distance, and the second group of gate electrode layers includes:
 a fifth gate electrode layer on one of the first to fourth gate electrode layer;   a sixth gate electrode layer stacked on the fifth gate electrode layer and covering only a portion of the fifth gate electrode layer on the connection region, thereby exposing a fifth pad region on the fifth gate electrode layer;   a seventh gate electrode layer stacked on the sixth gate electrode layer and covering only a portion of the sixth gate electrode layer on the connection region, thereby exposing a sixth pad region on the sixth gate electrode layer; and   a eighth gate electrode layer stacked on the seventh gate electrode layer and covering only a portion of the seventh gate electrode layer on the connection region, thereby exposing a seventh pad region on the seventh gate electrode layer and a eighth pad region on the eighth gate electrode layer respectively.   
     
     
         7 . The vertical memory device of  claim 6 , wherein the second distance is shorter than the first distance. 
     
     
         8 . The vertical memory device of  claim 7 , wherein the second group of electrode layers and the first group of electrode layers combined together form a second stepped structure in the first horizontal direction. 
     
     
         9 . The vertical memory device of  claim 8 , wherein further including fourth to eighth contact plugs formed vertically on the fourth to eighth pad regions respectively. 
     
     
         10 . The vertical memory device of  claim 9 , wherein each of the plurality of channel columns includes an epitaxial layer at a lower portion of the plurality of channel columns. 
     
     
         11 . The vertical memory device of  claim 10 , wherein an upper surface of each of the plurality of epitaxial layers is higher than an upper surface of a lowermost gate electrode layer among the plurality of gate electrode layers. 
     
     
         12 . The vertical memory device of  claim 11 , wherein each of the plurality of channel columns include a gate insulating layer, and the gate insulating layer includes an electric charge trap layer. 
     
     
         13 . The vertical memory device of  claim 12 , wherein the connection region extends at least 10 μm, but no longer than 28 μm from the cell array region to the connection region. 
     
     
         14 . The vertical memory device of  claim 12 , wherein a ratio of a length of the connection region along the first horizontal direction to the height of the plurality of gate electrode layers on the cell array region is greater than one and smaller than eight. 
     
     
         15 . A vertical memory device comprising:
 a substrate having a cell array region and a connection region adjacent to the cell array region;   a plurality of gate electrode layers stacked on the substrate in a vertical direction, the plurality of gate electrode layers including a first group of gate electrode layers which extends in a first horizontal direction from the cell array region to the connection region, each of the first group of gate electrode layers being spaced apart from each other by an insulating layer, and   a plurality of channel columns passing through the plurality of gate electrode layers in the vertical direction on the cell array region,   wherein the first group of gate electrode layers includes first to fourth gate electrode layers on which first to fourth pad regions are formed respectively,   wherein each of the first group of gate electrode layers extends as long as a first distance from the cell array region to the connection region, thereby forming an aligned edges on the connection region,   wherein the vertical memory device further includes first to fourth contact plugs formed vertically on the first to fourth pad regions respectively,   wherein a number of the plurality of gate electrode layers is equal to or greater than sixty and smaller than two hundreds,   wherein a height of the plurality of gate electrode layers on the cell array region is greater than 3.5 μm and less than 10 μm in the vertical direction, and   wherein a ratio of connection region length along the first horizontal direction to the height of the plurality of gate electrode layers on the cell array region is greater than 1 and smaller than 8.   
     
     
         16 . The vertical memory device of  claim 15 , wherein the first to fourth gate electrode layers combined together form a first stepped structure in a second horizontal direction which is perpendicular to the first horizontal direction. 
     
     
         17 . The vertical memory device of  claim 16 , wherein the first pad region locates lower than the second pad region, the second pad region locates lower than the third pad region, and the third pad region locates lower than the fourth pad region respectively. 
     
     
         18 . The vertical memory device of  claim 17 , wherein the plurality of gate electrode layers further include a second group of gate electrode layers stacked on the substrate and extending as long as a second distance from the cell array region to the connection region, the second distance is different from the first distance. 
     
     
         19 . The vertical memory device of  claim 18 , wherein the second distance is shorter than the first distance. 
     
     
         20 . The vertical memory device of  claim 19 , wherein the second group of electrode layers and the first group of electrode layers combined together form a second stepped structure in the first horizontal direction.