Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same

Abstract

A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

1 . A semiconductor chip package, comprising:
 a semiconductor chip disposed on a substrate,
 wherein the semiconductor chip has a first surface and a second surface, and 
 wherein the first surface of the semiconductor chip is connected to the substrate; and 
   a leadframe that includes a first lead and a second lead,
 wherein the first lead of the leadframe is directly attached to the second surface of the semiconductor chip, and 
 wherein the second lead of the leadframe is directly attached to the substrate. 
   
     
     
         2 . The semiconductor chip package of  claim 1 , wherein the semiconductor chip is a power switch. 
     
     
         3 . The semiconductor chip package of  claim 1 , wherein the first lead includes at least two leads that are aligned along substantially parallel directions. 
     
     
         4 . The semiconductor chip package of  claim 1 , wherein the second lead includes at least two leads that are aligned along substantially parallel directions. 
     
     
         5 . The semiconductor chip package of  claim 1 , wherein the semiconductor chip is a first semiconductor chip and a first portion of the first lead is directly attached to the second surface of the first semiconductor chip, and
 wherein the semiconductor chip package further comprises a second semiconductor chip having a third surface and a fourth surface,
 wherein the third surface of the second semiconductor chip is connected to the substrate, and 
   wherein a second portion of the first lead is directly attached to the fourth surface of the second semiconductor chip.   
     
     
         6 . The semiconductor chip package of  claim 5 , wherein the first semiconductor chip is a transistor and the second semiconductor chip is a diode,
 wherein the diode is electrically connected in parallel with the transistor.   
     
     
         7 . The semiconductor chip package of  claim 5 , wherein a third portion of the first lead extends below the second and fourth surfaces towards the substrate. 
     
     
         8 . The semiconductor chip package of  claim 5 , wherein the semiconductor chip package further comprises a third semiconductor chip having a fifth surface and a sixth surface,
 wherein the fifth surface of the third semiconductor chip is connected to the substrate, and   wherein a third portion of the first lead is directly attached to the sixth surface of the third semiconductor chip.   
     
     
         9 . The semiconductor chip package of  claim 8 , wherein the first semiconductor chip is a first transistor, the second semiconductor chip is a second transistor, and the third semiconductor chip is a diode,
 wherein the first transistor is connected in parallel with the second transistor and the diode, and   wherein the second transistor is connected in parallel with the diode.   
     
     
         10 . The semiconductor chip package of  claim 5 , wherein the first surface of the first semiconductor chip, the second lead, and the third surface of the second semiconductor chip are connected to a first portion of the substrate, and
 wherein the semiconductor chip package further comprises:
 a third semiconductor chip having a fifth surface and a sixth surface,
 wherein the fifth surface of the third semiconductor chip is connected to a second portion of the substrate, 
 wherein a first portion of a third lead of the leadframe is directly attached to the sixth surface of the third semiconductor chip; and 
 
 a fourth semiconductor chip having a seventh surface and an eighth surface,
 wherein the seventh surface of the fourth semiconductor chip is connected to the second portion of the substrate, 
 wherein a second portion of the third lead is directly attached to the eighth surface of the fourth semiconductor chip, 
 wherein the first portion of the substrate and the second portion of the substrate are electrically isolated from each other. 
 
   
     
     
         11 . The semiconductor chip package of  claim 10 , wherein a fourth lead of the leadframe is directly attached to the second portion of the substrate,
 wherein the fourth lead is connected to the first lead.   
     
     
         12 . The semiconductor chip package of  claim 10 , wherein the first semiconductor chip is a first transistor, the second semiconductor chip is a first diode, the third semiconductor chip is a second transistor, and the fourth semiconductor chip is a second diode,
 wherein the first transistor is electrically connected in parallel with the first diode, and   wherein the second transistor is electrically connected in parallel with the second diode.   
     
     
         13 . The semiconductor chip package of  claim 10 , wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are connected to form a half-bridge circuit. 
     
     
         14 . A method for fabricating a semiconductor chip package, the method comprising:
 disposing a semiconductor chip on a substrate,
 wherein the semiconductor chip has a first surface and a second surface, and 
 wherein the first surface of the semiconductor chip is connected to the substrate; 
   attaching a first lead of a leadframe to the second surface of the semiconductor chip; and   attaching second lead of the leadframe to the substrate.   
     
     
         15 . The method of  claim 14 , further comprising disposing an encapsulant on the substrate, the semiconductor chip, and a portion of the leadframe. 
     
     
         16 . The method of  claim 14 , wherein at least one of the first lead and the second lead includes at least two leads that are aligned along substantially parallel directions. 
     
     
         17 . The method of  claim 14 , wherein the first lead of the leadframe is attached to the second surface of the semiconductor chip concurrently with the second lead of the leadframe being attached to the substrate. 
     
     
         18 . The method of  claim 14 , wherein the semiconductor chip is a power switch. 
     
     
         19 . The method of  claim 14 , wherein the semiconductor chip is a first semiconductor chip and a first portion of the first lead is attached to the second surface of the first semiconductor chip, and
 wherein the method further comprises:
 disposing a second semiconductor chip on the substrate,
 wherein the second semiconductor chip has a third surface and a fourth surface, and 
 wherein the third surface of the semiconductor chip is connected to the substrate; and 
 
 attaching a second portion of the first lead to the fourth surface of the second semiconductor chip. 
   
     
     
         20 . An electronic module, comprising:
 at least one semiconductor chip package comprising:
 a semiconductor chip disposed on a substrate,
 wherein a first surface of the semiconductor chip is connected to the substrate; and 
 
 a leadframe that includes a first lead and a second lead,
 wherein the first lead of the leadframe is directly attached to a second surface of the semiconductor chip, and 
 wherein the second lead of the leadframe is directly attached to the substrate.