US2019097059A1PendingUtilityA1

Semiconductor device

Assignee: SHARP KKPriority: Sep 28, 2017Filed: Sep 27, 2018Published: Mar 28, 2019
Est. expirySep 28, 2037(~11.2 yrs left)· nominal 20-yr term from priority
G02F 1/134363G02F 1/1368H01L 29/7869H01L 29/24G02F 2001/13685H01L 29/267H01L 29/78633H01L 27/1225H01L 29/78696H10D 62/80H10D 30/475H10D 30/473H10D 30/472H10D 99/00H10D 86/423H10D 86/60H10D 62/82H10D 30/6757H10D 30/6734H10D 30/6723H10D 86/421H10D 30/6755H10D 86/40G02F 1/134372G02F 1/13685
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In a semiconductor device, at least one thin-film transistor includes a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode. The semiconductor layer has a multilayer structure that includes a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer. The first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer. The plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer. The plurality of channel formation layers each have a mobility higher than that of the at least one middle layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate; and   a plurality of thin-film transistors supported by the substrate,   
       wherein
 at least one of the plurality of thin-film transistors includes a semiconductor layer, a gate electrode, a gate insulating layer provided between the gate electrode and the semiconductor laver, and a source electrode and a drain electrode electronically connected to the semiconductor layer, 
 the semiconductor layer has a multilayer structure including
 a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and 
 at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer, 
 
 the first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer, 
 the plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer, and the plurality of channel formation layers each have a mobility higher than that of the at least one middle layer. 
 
     
     
         2 . The semiconductor device of  claim 1 , wherein
 the plurality of channel formation layers and the at least one middle layer all include a first metal element and a second metal element, the first metal element is In, and the second metal element is one of Ga and Zn,   the atomic proportion of the first metal element to all metal elements contained in each of the plurality of channel formation layers is different from the atomic proportion of the first metal element to all metal elements contained in the at least one middle layer,   in each of the plurality of channel formation layers, the atomic proportion of the first metal element to all the metal elements is greater than or equal to the atomic proportion of the second metal element to all the metal elements, and   in the at least one middle layer, the atomic proportion of the first metal element to all the metal elements is smaller than or equal to the atomic proportion of the second metal element to all the metal elements.   
     
     
         3 . A semiconductor device comprising:
 a substrate; and   a plurality of thin-film transistors supported by the substrate,   
       wherein
 at least one of the plurality of thin-film transistors includes a semiconductor layer, a gate electrode, a gate insulating layer provided between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electronically connected to the semiconductor layer, 
 the semiconductor layer has a multilayer structure including
 a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and 
 at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer, 
 
 the first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer, 
 the plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer including a first metal element and a second metal element, the first metal element is In, and the second metal element is one of Ga and Zn, 
 the atomic proportion of the first metal element to all metal elements contained in in each of the plurality of channel formation layers is different from the atomic proportion of the first metal element to all metal elements contained in the at least one middle layer, 
 in each of the plurality of channel formation layers, the atomic proportion of the first metal element to all the metal elements is greater than or equal to the atomic proportion of the second metal element to all the metal elements, and 
 in the at least one middle layer, the atomic proportion of the first metal element to all the metal elements is smaller than or equal to the atomic proportion of the second metal element to all the metal elements. 
 
     
     
         4 . The semiconductor device of  claim 1 , wherein
 the first channel formation layer and the second channel formation layer have substantially the same composition.   
     
     
         5 . The semiconductor device of  claim 1 , wherein
 the first middle layer is in contact with the first channel formation layer and the second channel formation layer.   
     
     
         6 . The semiconductor device of  claim 1 , wherein
 the first channel formation layer and the second channel formation layer each have a thickness smaller than a thickness of the first middle layer.   
     
     
         7 . The semiconductor device of  claim 1 , wherein
 the plurality of channel formation layers further include a third channel formation layer provided on an opposite side of the second channel formation layer from the first middle layer, and   the at least one middle layer further includes a second middle layer provided between the third channel formation layer and the second channel formation layer.   
     
     
         8 . The semiconductor device of  claim 1 , wherein
 the gate electrode is disposed between the semiconductor layer and the substrate.   
     
     
         9 . The semiconductor device of  claim 8 , wherein
 the at least one thin-film transistor has a channel-etch structure, and   the multilayer structure of the semiconductor layer includes a protective layer as an uppermost layer, and the protective layer is an oxide semiconductor layer having a mobility lower than those of the plurality of channel formation layers.   
     
     
         10 . The semiconductor device of  claim 8 , wherein
 the at least one thin-film transistor has an etch-stop structure.   
     
     
         11 . The semiconductor device of  claim 8 , wherein
 the at least one thin-film transistor further includes an upper electrode provided on the semiconductor layer with an upper insulating layer interposed therebetween.   
     
     
         12 . The semiconductor device of  claim 11 , wherein
 one of the plurality of channel formation layers is an uppermost layer of the multilayer structure, and is in contact with the upper insulating layer.   
     
     
         13 . The semiconductor device of  claim 1 , wherein
 the gate electrode is disposed on an opposite side of the semiconductor layer from the substrate with the gate insulating layer interposed between the gate electrode and the semiconductor layer.   
     
     
         14 . The semiconductor device of  claim 13 , wherein
 the gate insulating layer is disposed on a portion of the semiconductor layer, and is located only between the semiconductor layer and the gate electrode,   the semiconductor device further includes an interlayer insulating layer covering the semiconductor layer, the gate electrode, and the gate insulating layer, and   the source electrode and the drain electrode are each disposed on the interlayer insulating layer, and are each in contact with the semiconductor layer in an opening provided in the interlayer insulating layer.   
     
     
         5 . The semiconductor device of  claim 13 , wherein
 the at least one thin-film transistor further includes
 a lower electrode provided between the substrate and the semiconductor layer, and 
 a lower insulating layer provided between the lower electrode and the semiconductor layer. 
   
     
     
         16 . The semiconductor device of claim  15 , wherein
 one of the plurality of channel formation layers is a lowermost layer of the multilayer structure, and is in contact with the lower insulating layer.   
     
     
         17 . The semiconductor device of  claim 1 , wherein
 the semiconductor device is an active matrix substrate having a display region including a plurality of pixels, and a non-display region other than the display region.   
     
     
         18 . The semiconductor device of  claim 17 , wherein
 the at least one thin-film transistor includes a pixel TFT provided at each of the plurality of pixels.   
     
     
         19 . The semiconductor device of  claim 17 , further comprising:
 a drive circuit provided in the non-display region, wherein   the at least one thin-film transistor includes a circuit TFT included in the drive circuit.   
     
     
         20 . The semiconductor device of  claim 1 , wherein
 the plurality of channel formation layers and the at least one middle layer all contain In, Ga, and Zn.

Join the waitlist — get patent alerts

Track US2019097059A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.