Transformational architecture for multi-layer systems

Abstract

The new architecture disclosed herein exploits advances in system and chip technologies to implement a scalable multi-port open network. Using System-on-a-Chip (SOCs) and/or Multi-Chip-Module (MCM) technology, the architecture is implemented to efficiently handle multi-port switching. The novelty lies in using multi-core computing model in the data, control and management planes of multi-port networking cards implemented as an elemental scalable system (ESS) comprising N number of Elemental Units (EUs). EUs comprise device arrays on an integrated circuit (IC) platform using integrated silicon photonics or discrete electro-optics. TX4M™ system architecture therefore includes multiple EUs, switch fabric, multi-core central processing unit (CPU), multi-port power management module with embedded programmable logic, a back plane interface (BPI) as well as selectable functions for front plane interface (FPI) implemented in FPGAs for integration of front plane interface optics on host or on pluggable modules.

1 . A power-efficient elemental scalable system (ESS) implementing a scalable multi-port network architecture, the system having a multi-port front-plane interface comprising an external array of network interface modules for receiving incoming network signals and transmitting outgoing network signals, each network interface module having a plurality of network ports, the system comprising:
 an array of physical layer devices implemented on an integrated circuit platform, each physical layer device coupled to a corresponding network interface module;   an array of link control layer devices implemented on the integrated circuit platform, each link control layer device coupled to a corresponding physical layer device;   a multi-core central processing unit (CPU) implemented on the integrated circuit platform coupled to the array of the link control layer devices, wherein the central processing unit is programmed to dynamically provision appropriate bandwidth to each network port in the multi-port network;   a switching fabric coupled to the array of the link control layer devices;   a back-plane interface coupled to the switching fabric,   wherein the switching fabric and the back-plane interface jointly control switching and routing of network paths in the multi-port network; and   a multi-port power management module coupled to the array of the link control layer devices, wherein the power management module intelligently manages power according to the dynamic bandwidth provisioning in each network port.   
     
     
         2 . The system of  claim 1 , wherein the scalable multi-port network architecture is compatible with the multi-layer open networking model. 
     
     
         3 . The system of  claim 2 , wherein the open networking model is suitable for telecommunication, data communication, cloud computing, data center switching, defense applications, or consumer applications. 
     
     
         4 . The system of  claim 1 , wherein the multi-port power management module comprises an array of sub-modules, each sub-module coupled to a corresponding link control layer device. 
     
     
         5 . The system of  claim 1 , wherein the integrated circuit platform uses one or more of the following semiconductor processing technologies: complementary metal oxide semiconductor (CMOS), Bi-CMOS, silicon germenium (SiGe), gallium arsenide (GaAs) based integrated and/or discrete components, photonic integrated circuits, and, silicon photonics. 
     
     
         6 . The system of  claim 1 , wherein the integrated circuit platform is implemented as a system-on-chip (SOC) wherein the array of physical layer devices and the array of link control layer devices are fabricated monolithically on a same substrate, and packaged together. 
     
     
         7 . The system of  claim 1 , wherein the integrated circuit platform is implemented as a multi-chip-module (MCM) wherein the array of physical layer devices and the array of link control layer devices are packaged separately, and/or hybridly integrated on a common substrate. 
     
     
         8 . The system of  claim 1 , wherein ‘X’ number of network ports are distributed between ‘N’ number of identical elemental units, each elemental unit comprising a physical layer device circuit unit, and a link control layer device circuit unit corresponding to an external network interface module. 
     
     
         9 . The system of  claim 8 , wherein each of the network interface modules in the front plane interface has ‘A’ number of ports arranged in a ‘a×b’ matrix configuration in the corresponding network interface module, such that the multiplication of ‘a’ and ‘b’ yields ‘A’. 
     
     
         10 . The system of  claim 8 , wherein the total area taken by the system and the power consumed by the system are both scaled down approximately by a factor of ‘N’ for ‘X’ number of network ports because of the integrated circuit implementation of the scalable architecture with ‘N’ number of identical elemental units. 
     
     
         11 . The system of  claim 1 , wherein the incoming network signals comprise optical signals, which are converted to electronic signals for conditioning and bandwidth provisioning purposes on the integrated circuit platform, and then re-converted into optical signals again for transmission. 
     
     
         12 . The system of  claim 1 , wherein the network interface modules comprise one or more of the following standardized pluggable fiber optic interfaces: RJ-45, XSFP+(variants of small form factor pluggable plus), Quad SFP (QSFP), CXX (variants of C-form factor pluggable). 
     
     
         13 . The system of  claim 1 , wherein the network interface modules comprise a combination of fiber optic, free-space optic and copper interfaces. 
     
     
         14 . The system of  claim 1 , wherein the multi-core CPU manages bandwidth partitioning functions. 
     
     
         15 . The system of  claim 14 , wherein the system further includes a memory management module that dynamically allocates the required amount of memory to each port based on the bandwidth partitioning.