Registering clock driver controlled decision feedback equalizer training process

Abstract

A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

What is claimed is: 
     
         1 . A driver circuit, comprising:
 a) an input to receive a control signal from a memory bus;   b) redriver circuitry to redrive the control signal to multiple memory chips;   c) a decision feedback equalizer (DFE) receiver circuit coupled between the input and the redriver circuitry, the DFE receiver circuit comprising a primary slicer circuit and a secondary slicer circuit;   d) a training controller to control a training process to determine a tap coefficient value for said DFE performed by the driver circuit, said training controller to control a sweep of tap coefficient values during said training and control a sweep of a voltage of one of said slicers during said training, said control signal compared against the voltage by said one of said slicers to determine its logical vale.   
     
     
         2 . The driver circuit of  claim 1  wherein the driver circuit is a register redriver circuit. 
     
     
         3 . The driver circuit of  claim 1  wherein the register redriver circuit is compatible with a Joint Electron Device Engineering Council (JEDEC) Double Data Rate (DDR) memory bus standard. 
     
     
         4 . The driver circuit of  claim 1  wherein the training controller is to control a sweep of the secondary slicer's threshold voltage during the training. 
     
     
         5 . The driver circuit of  claim 4  wherein the driver circuit further comprises a voltage divider circuit to control the control signal's reference voltage. 
     
     
         6 . The driver circuit of  claim 1  wherein the training controller is to receive, from a memory controller, ranges and increments of the tap coefficient and the voltage for the sweeps. 
     
     
         7 . The driver circuit of  claim 1  wherein the driver circuit is disposed on a dual in line memory module (DIMM). 
     
     
         8 . The driver circuit of  claim 1  wherein the driver circuit is a component in a computing system. 
     
     
         9 . A memory controller, comprising:
 a) an interface to a double data rate (DDR) memory bus;   b) test pattern generation logic circuitry to generate test patterns to determine a coefficient tap value for a distributed feedback analyzer (DFE);   c) a control circuit to perform a DFE coefficient tap training process for the DFE in which a driver circuit that is coupled to the memory controller through the interface includes the DFE and controls sweeps of the coefficient tap value and a voltage of a slicer that receives the test patterns during the DFE coefficient tap training process, the control circuit to determine range and/or increment information for the sweeps and send the information to the driver circuit.   
     
     
         10 . The memory controller of  claim 9  wherein the DDR memory bus is compatible with a JEDEC DDR memory bus standard. 
     
     
         11 . The memory controller of  claim 10  wherein the driver circuit is coupled to the interface by way of a command address (CA) signal line. 
     
     
         12 . The memory controller of  claim 9  wherein the control circuit determines the range and/or increment information from testing results sent to the memory controller by the driver circuit. 
     
     
         13 . The memory controller of  claim 9  wherein the control circuit is to repeatedly determine new range and/or increment information for each of multiple DFE coefficient taps of the DFE. 
     
     
         14 . The memory controller of  claim 9  wherein the control circuit is to determine a first estimate of DFE tap coefficients before finally determining a particular DFE tap coefficient. 
     
     
         15 . The memory controller of  claim 1  wherein the memory controller is embedded within a computing system. 
     
     
         16 . A method performed by a driver circuit, comprising:
 receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit;   controlling the testing sequence, the testing sequence comprising sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit; and,   sending results of the testing sequence to the memory controller, the results to determine a value for the DFE tap coefficient.   
     
     
         17 . The method of  claim 16  wherein the driver circuit is a registering driver circuit of a DDR memory bus. 
     
     
         18 . The method of  claim 17  wherein the DDR memory bus is a JEDEC compliant DDR memory bus. 
     
     
         19 . The method of  claim 18  wherein the DFE circuit is coupled to receive a CA signal of the DDR memory bus. 
     
     
         20 . The method of  claim 16  wherein the configuration specifies ranges and increments of the sweeps.