High-resolution power electronics measurements

Abstract

Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

1 .- 25 . (canceled) 
     
     
         26 . A method comprising:
 estimating, by an attenuation circuit, a drain voltage of a high voltage transistor while the high voltage transistor is turned on;   sensing, by a current sense circuit, a current conducted by the high voltage transistor while the high voltage transistor is turned on;   determining a first slope of the estimated drain voltage over a time period;   determining a second slope of the sensed current over the time period; and   determining an on-state impedance value of the high voltage transistor based on a ratio of the first slope over the second slope.   
     
     
         27 . The method of  claim 26 , wherein the estimating includes coupling a drain terminal of the high voltage transistor to a drain terminal of a clamp transistor in the attenuation circuit. 
     
     
         28 . The method of  claim 26 , wherein the high voltage transistor includes a high electron mobility transistor (HEMT). 
     
     
         29 . The method of  claim 28 , wherein the HEMT is selected from a group consisting of a gallium nitride (GaN) transistor, an aluminum gallium nitride (AlGaN) transistor, and combinations thereof. 
     
     
         30 . The method of  claim 26 , wherein the high voltage transistor includes a silicon carbide transistor. 
     
     
         31 . The method of  claim 26 , wherein the determining the first slope of the estimated drain voltage includes:
 digitizing samples of the estimated drain voltage over the time period; and   determining the first slope based on at least two of the digitized samples.   
     
     
         32 . The method of  claim 26 , wherein the determining the second slope of the sensed current includes:
 digitizing samples of the sensed current over the time period; and   determining the second slope based on at least two of the digitized samples.   
     
     
         33 . The method of  claim 26 , wherein the estimating the drain voltage includes:
 attenuating, by the attenuation circuit, the drain voltage of the high voltage transistor to generate a clamp voltage; and   amplifying, by an amplification circuit, the clamp voltage to generate the estimated drain voltage.   
     
     
         34 . The method of  claim 33 , wherein the attenuating the drain voltage includes:
 generating, by a clamp transistor of the attenuation circuit, a sense voltage sensed from a drain terminal of the high voltage transistor; and   dividing, by a voltage divider of the attenuation circuit, the sense voltage to generate the clamp voltage.   
     
     
         35 . The method of  claim 26 , wherein:
 the sensing the current includes sensing, by the current sense circuit, a voltage across a sense resistor coupled between a source terminal of the high voltage transistor and a ground reference terminal; and   the determining the on-state impedance value includes subtracting a resistance value of the sense resistor from the ratio of the first slope over the second slope.   
     
     
         36 . A device comprising:
 a high voltage transistor having a drain terminal, a source terminal, and a gate terminal;   a clamp transistor having a drain terminal coupled to the drain terminal of the high voltage transistor, a source terminal isolated from the source terminal of the high voltage transistor, and a gate terminal isolated from the gate terminal of the high voltage transistor; and   a Zener diode having an anode coupled to a ground reference terminal, and a cathode coupled to the source terminal of the clamp transistor.   
     
     
         37 . The device of  claim 36 , wherein the high voltage transistor includes a high electron mobility transistor (HEMT). 
     
     
         38 . The device of  claim 38 , wherein the HEMT is selected from a group consisting of a gallium nitride (GaN) transistor, an aluminum gallium nitride (AlGaN) transistor, and combinations thereof. 
     
     
         39 . The device of  claim 36 , wherein the high voltage transistor includes a silicon carbide transistor. 
     
     
         40 . The device of  claim 36 , wherein the clamp transistor includes an n-channel MOSFET transistor. 
     
     
         41 . The device of  claim 36 , wherein:
 the gate terminal of the high voltage transistor is configured to receive a gate driver signal; and   the gate terminal of the clamp transistor is configured to receive a bias voltage for attenuating, at the source terminal of the clamp transistor, a drain voltage of the high voltage transistor.   
     
     
         42 . The device of  claim 36 , further comprising:
 a gate driver circuit coupled to the gate terminal of the high voltage transistor; and   a biasing circuit coupled to the gate terminal of the clamp transistor.   
     
     
         43 . A device comprising:
 a gallium nitride (GaN) transistor having a drain terminal, a source terminal, and a gate terminal;   a clamp transistor having a drain terminal coupled to the drain terminal of the GaN transistor, a source terminal isolated from the source terminal of the GaN transistor, and a gate terminal isolated from the gate terminal of the GaN transistor; and   a Zener diode having an anode coupled to a ground reference terminal, and a cathode coupled to the source terminal of the clamp transistor.   
     
     
         44 . The device of  claim 43 , further comprising:
 a voltage divider coupled between the source terminal of the clamp transistor and the ground reference terminal, the voltage divider having a divided voltage node; and   a capacitor coupled between the source terminal of the clamp transistor and the divided voltage node.   
     
     
         45 . The device of  claim 43 , further comprising:
 a gate driver circuit coupled to the gate terminal of the high voltage transistor; and   a biasing circuit coupled to the gate terminal of the clamp transistor.