Compound semiconductor field effect transistor with self-aligned gate

Abstract

A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

What is claimed is: 
     
         1 . A method of making a compound semiconductor field effect transistor (FET), comprising:
 forming a cavity in a compound semiconductor active layer of the compound semiconductor FET through an opening in a first dielectric layer on the compound semiconductor active layer to form a recessed gate region;   etching through an oxide layer in the opening within the first dielectric layer and in the cavity of the recessed gate region to create a base gate opening;   filling the base gate opening with a first conductive gate material to create a base gate; and   plating a second conductive gate material on the base gate to create a head gate electrically contacting the base gate.   
     
     
         2 . The method of  claim 1 , in which forming the cavity comprises:
 depositing a spacer material on a hard mask on the compound semiconductor active layer, the spacer material surrounding a dummy base gate on the hard mask;   etching the spacer material to form a pair of spacers on sidewalls of the dummy base gate;   etching the dummy base gate to form a gate spacer opening exposing the hard mask on the compound semiconductor active layer;   etching the hard mask to expose the compound semiconductor active layer; and   selectively etching the compound semiconductor active layer and stopping on an etch stop layer.   
     
     
         3 . The method of  claim 2 , further comprising:
 etching the etch stop layer to expose a channel layer to open the cavity in the compound semiconductor active layer; and   lining the cavity and the gate spacer opening with a passivation layer.   
     
     
         4 . The method of  claim 2 , further comprising lining the cavity and the gate spacer opening with a passivation layer. 
     
     
         5 . The method of  claim 4 , further comprises:
 depositing a liquid oxide material on the passivation layer that lines the gate spacer opening and the cavity; and   baking the liquid oxide material to form the oxide layer.   
     
     
         6 . The method of  claim 2 , further comprising:
 depositing a second dielectric layer on the first dielectric layer and on the head gate, in which the second dielectric layer is different from the first dielectric layer; and   forming source/drain contacts to ohmic contacts electrically coupled to source/drain regions of the compound semiconductor FET through the first dielectric layer and the second dielectric layer.   
     
     
         7 . The method of  claim 2 , in which the depositing the first conductive gate material comprises depositing the first conductive gate material on an exposed portion of a channel layer to form the base gate. 
     
     
         8 . The method of  claim 1 , in which etching through the oxide layer comprises:
 planarizing the recessed gate region by the oxide layer to form a planarized dielectric layer;   fabricating a spacer on the planarized dielectric layer; and   etching through the planarized dielectric layer based on the spacer to create the base gate opening.   
     
     
         9 . The method of  claim 8 , in which:
 etching through the oxide layer comprises etching through a passivation layer at a base of the cavity based on the spacer to create an elongated base gate opening; and   filling comprises filling the elongated base gate opening with the first conductive gate material to create an extended base gate, the extended base gate and the head gate comprising a Schottky gate.   
     
     
         10 . The method of  claim 1 , further comprising:
 integrating the compound semiconductor FET with a power amplifier; and   integrating the power amplifier into a wireless transceiver, the wireless transceiver incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.