Sawtooh electric field drift region structure for planar and trench power semiconductor devices

Abstract

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

I claim: 
     
         1 . A semiconductor power device comprising:
 a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure;   a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns; and   the source, drain and gate columns are formed with a closed cell layout configuration comprising a plurality of transistor close cells across a horizontal direction of the semiconductor substrate and the drain column of the first conductivity type is disposed at a center of the closed cells.   
     
     
         2 . The semiconductor power device of  claim 1  wherein:
 the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer. 
 
     
     
         3 . The semiconductor power device of  claim 1  wherein:
 the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer. 
 
     
     
         3 . The semiconductor power device of  claim 2  wherein:
 the gate column extends downwardly into the intermediate semiconductor layer to constitute a built-in gate-drain avalanche clamp diode from a combination of the bottom semiconductor layer through the intermediate semiconductor layer to the gate column. 
 
     
     
         4 . The semiconductor power device of  claim 2  wherein:
 the source column extends into said intermediate semiconductor layer and further comprises a bipolar suppressing region in the intermediate semiconductor layer at the bottom of the source column; said bipolar suppressing region is doped with the second conductivity type. 
 
     
     
         5 . The semiconductor power device of  claim 2  wherein:
 the gate column extends deeper than the source column. 
 
     
     
         6 . The semiconductor power device of  claim 2  wherein:
 said source, drain and gate columns form a JFET, and wherein the semiconductor power device further comprises a MOSFET connected in a cascode circuit configuration with said JFET. 
 
     
     
         7 . The semiconductor power device of  claim 6  wherein:
 said MOSFET is integrated with said JFET at the device cell level. 
 
     
     
         8 . The device of  claim 7 , wherein:
 said MOSFET further comprises a source region, a body region, a gate, and a drain region wherein the source region extends along a direction parallel to the source column and is separated therefrom with the body region disposed between the source region and the source column.   
     
     
         9 . The device of  claim 8  wherein:
 said gate of the MOSFET is configured to form an inversion channel between said source region of the MOSFET and said source column. 
 
     
     
         10 . A semiconductor power device comprising:
 a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure;   a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns; and   the source, drain and gate columns are arranged as stripes extending horizontally across the semiconductor substrate.   
     
     
         11 . The semiconductor power device of  claim 10  wherein:
 the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer. 
 
     
     
         12 . The semiconductor power device of  claim 10  wherein:
 the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer. 
 
     
     
         13 . The semiconductor power device of  claim 11  wherein:
 the gate column extends downwardly into the intermediate semiconductor layer to constitute a built-in gate-drain avalanche clamp diode from a combination of the bottom semiconductor layer through the intermediate semiconductor layer to the gate column. 
 
     
     
         14 . The semiconductor power device of  claim 11  wherein:
 the source column extends into said intermediate semiconductor layer and further comprises a bipolar suppressing region in the intermediate semiconductor layer at the bottom of the source column; said bipolar suppressing region is doped with the second conductivity type. 
 
     
     
         15 . The semiconductor power device of  claim 11  wherein:
 the gate column extends deeper than the source column. 
 
     
     
         16 . The semiconductor power device of  claim 11  wherein:
 said source, drain and gate columns form a JFET, and wherein the semiconductor power device further comprises a MOSFET connected in a cascode circuit configuration with said JFET. 
 
     
     
         17 . The semiconductor power device of  claim 16  wherein:
 said MOSFET is integrated with said JFET at the device cell level. 
 
     
     
         18 . The device of  claim 16 , wherein:
 said MOSFET further comprises a source region, a body region, a gate, and a drain region wherein the source region extends along a direction parallel to the source column and is separated therefrom with the body region disposed between the source region and the source column.   
     
     
         19 . The device of  claim 17  wherein:
 said gate of the MOSFET is configured to form an inversion channel between said source region of the MOSFET and said source column. 
 
     
     
         20 . The semiconductor power device of claim  23  further comprising:
 the bottom semiconductor layer disposed under the super junction structure, wherein 
 one of said gate columns or said drain columns interfaces as a PN junction with said bottom semiconductor layer thus constitutes said built-in gate-drain avalanche clamp diode near the bottom surface of the semiconductor substrate.