Bonding pad architecture using capacitive deep trench isolation (cdti) structures for electrical connection

Abstract

A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

1 . An integrated circuit, comprising:
 a semiconductor substrate having a back side surface and a front side surface;   a plurality of metallization levels including metal lines and vias;   a plurality of capacitive deep trench isolation structures, wherein each capacitive deep trench isolation structure extends completely through the semiconductor substrate from the front side surface to the back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;   electrical contacts between the conductive regions at first ends of the plurality of capacitive deep trench isolation structures to a first metallization level of said plurality of metallization levels; and   a bonding pad structure located at the back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the conductive regions at second ends of the plurality of capacitive deep trench isolation structures.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the plurality of capacitive deep trench isolation structures are arranged in an intersecting pattern of rows and columns. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the plurality of capacitive deep trench isolation structures are arranged in a pattern of parallel rows. 
     
     
         4 . The integrated circuit of  claim 3 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width, and wherein the rows extend parallel to the lengths of the capacitive deep trench isolation structures. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the plurality of capacitive deep trench isolation structures are arranged in a pattern of parallel columns. 
     
     
         6 . The integrated circuit of  claim 5 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width, and wherein the columns extend parallel to the lengths of the capacitive deep trench isolation structures. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the bonding pad structure comprises a metal liner and a metal block over the metal liner, the metal liner being directly physically and electrically connected to the conductive regions at second ends of the plurality of capacitive deep trench isolation structures. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the ends of the plurality of capacitive deep trench isolation structures project beyond the back side surface of the semiconductor substrate. 
     
     
         9 . The integrated circuit of  claim 1 , wherein the ends of the plurality of capacitive deep trench isolation structures are coplanar with the back side surface of the semiconductor substrate. 
     
     
         10 . The integrated circuit of  claim 1 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width. 
     
     
         11 . The integrated circuit of  claim 1 , wherein the bonding pad structure comprises a first metal liner, a layer of tungsten over the first metal liner, a second metal liner over the layer of tungsten and a metal block over the layer of tungsten, the first metal liner being directly physically and electrically connected to the conductive regions at second ends of the plurality of capacitive deep trench isolation structures. 
     
     
         12 . The integrated circuit of  claim 11 , wherein the first metal liner and the layer of tungsten over the first metal liner are further positioned at a location at the back side surface spaced apart from the bonding pad structure, and further comprising an additional pad structure in direct contact with the layer of tungsten at said location. 
     
     
         13 - 20 . (canceled) 
     
     
         21 . An integrated circuit, comprising:
 a semiconductor substrate having a back side surface and a front side surface;   a plurality of metallization levels including metal lines and vias;   a plurality of capacitive deep trench isolation structures, wherein each capacitive deep trench isolation structure extends completely through the semiconductor substrate from the front side surface to the back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;   electrical contacts between first ends of the conductive regions for the plurality of capacitive deep trench isolation structures to a first metallization level of said plurality of metallization levels; and   a bonding pad structure located at the back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the second ends of the conductive regions for the plurality of capacitive deep trench isolation structures.   
     
     
         22 . The integrated circuit of  claim 21 , wherein the plurality of capacitive deep trench isolation structures are arranged in an intersecting pattern of rows and columns. 
     
     
         23 . The integrated circuit of  claim 21 , wherein the plurality of capacitive deep trench isolation structures are arranged in a pattern of parallel rows. 
     
     
         24 . The integrated circuit of  claim 23 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width, and wherein the rows extend parallel to the lengths of the capacitive deep trench isolation structures. 
     
     
         25 . The integrated circuit of  claim 21 , wherein the plurality of capacitive deep trench isolation structures are arranged in a pattern of parallel columns. 
     
     
         26 . The integrated circuit of  claim 25 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width, and wherein the columns extend parallel to the lengths of the capacitive deep trench isolation structures. 
     
     
         27 . The integrated circuit of  claim 21 , wherein the bonding pad structure comprises a metal liner and a metal block over the metal liner, the metal liner being directly physically and electrically connected to the second ends of the conductive regions for the plurality of capacitive deep trench isolation structures. 
     
     
         28 . The integrated circuit of  claim 21 , wherein the ends of the plurality of capacitive deep trench isolation structures project beyond the back side surface of the semiconductor substrate. 
     
     
         29 . The integrated circuit of  claim 21 , wherein each capacitive deep trench isolation structure has a width and a length, and wherein the length is greater than the width.