Capacitive field sensor with sigma-delta modulator

Abstract

A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation circuit is coupled to the modulation capacitor to selectively discharge the modulation capacitor in response to the modulation signal.

What is claimed is: 
     
         1 - 6 . (canceled) 
     
     
         7 . A configurable analog processing circuit, comprising:
 a programmable interconnect configurable to enable routing between a first and second signal paths;   a plurality of analog circuit blocks formed in a same integrated circuit comprising inputs and outputs coupled to the first and second signal paths, each analog block providing at least one analog function, wherein the programmable interconnect comprises a plurality of switches coupled between the plurality of analog circuit blocks and ports that provide signal connections for the same integrated circuit, and wherein at least two analog circuit blocks are interconnected to provide at least another analog function;   a plurality of digital circuit blocks formed in the same integrated circuit comprising inputs and outputs coupled to the first and second signal paths; and   an internal input/output (I/O) bus comprising bus lines coupled to the first and second signal paths.   
     
     
         8 . The configurable analog processing circuit of  claim 7 , wherein the programmable interconnect is configurable to connect multiple analog circuit blocks with one another in series. 
     
     
         9 . The configurable analog processing circuit of  claim 7 , wherein each analog circuit block is programmable to perform at least one of a plurality of different analog functions. 
     
     
         10 . The configurable analog processing circuit of  claim 7 , wherein:
 the same integrated circuit comprises at least one port as a signal connection point; and   the programmable interconnect is configurable to connect the at least one port to any of the plurality of analog circuit blocks.   
     
     
         11 . The configurable analog processing circuit of  claim 10 , wherein the programmable interconnect is configurable to provide an analog signal input path from the at least one port to any of the plurality of analog circuit blocks. 
     
     
         12 . The configurable analog processing circuit of  claim 10 , wherein the programmable interconnect is configurable to provide an analog signal output path from any of the plurality of analog circuit blocks to the at least one port. 
     
     
         13 . The configurable analog processing circuit of  claim 7 , wherein at least one of the plurality of analog circuit blocks is coupled to at least one of the plurality of digital circuit blocks through the programmable interconnect to provide at least one mixed-signal function. 
     
     
         14 . The configurable analog processing circuit of  claim 7 , wherein at least one of the plurality of analog circuit blocks is configurable to perform a first function in a first configuration and a second function in a second configuration. 
     
     
         15 . The configurable analog processing circuit of  claim 7 , wherein the programmable interconnect has a first analog portion and a second digital portion. 
     
     
         16 . A method comprising:
 coupling an internal input/output (I/O) bus to a programmable interconnect;   coupling at least one of a plurality of programmable analog blocks to the programmable interconnect;   performing a first operation on a first signal received at the internal I/O bus by the at least one of the plurality of programmable analog blocks; and   performing at least a second operation on a second signal received at the internal I/O bus by at least two of the plurality of programmable analog blocks.   
     
     
         17 . The method of  claim 16 , wherein the at least two of the plurality of programmable analog blocks comprise the at least one of the plurality of programmable analog blocks. 
     
     
         18 . The method of  claim 16 , wherein performing the at least the second operation comprises performing a first sub-operation with a second analog block of the plurality of programmable analog blocks and performing a second sub-operation with a third analog block of the plurality of programmable analog blocks. 
     
     
         19 . The method of  claim 18 , where the at least one of the plurality of programmable analog blocks is the same as either the second analog block or the third analog block. 
     
     
         20 . The method of  claim 18 , further comprising coupling the second analog block to the third analog block through an intra-block routing. 
     
     
         21 . The method of  claim 16 , further comprising coupling at least one digital block of a plurality of programmable digital blocks to the programmable interconnect to perform at least one digital function. 
     
     
         22 . The method of  claim 16 , further comprising coupling the internal I/O bus to a port for receiving signals. 
     
     
         23 . A mixed-signal array comprising:
 a programmable interconnect configurable to enable multiple signal routing on first and second signal paths;   an array of analog circuit blocks formed in a same integrated circuit comprising inputs and outputs coupled to the first and second signal paths, each analog circuit block providing at least one analog function, wherein the programmable interconnect comprises a plurality of switches coupled between the array of analog circuit blocks and ports that provide signal connections for the same integrated circuit, and wherein at least two analog circuit blocks are interconnected to provide at least another analog function;   an array of digital circuit blocks formed in the same integrated circuit comprising inputs and outputs coupled to the first and second paths; and   an internal input/output (I/O) bus comprising bus lines coupled to the first and second signal paths.   
     
     
         24 . The mixed-signal array of  claim 23 , wherein the programmable interconnect is configurable to connect multiple analog circuit blocks in series with one another. 
     
     
         25 . The mixed-signal array of  claim 23 , wherein each analog circuit block is programmable to perform at least one of a plurality of different analog functions. 
     
     
         26 . The mixed-signal array of  claim 23 , wherein at least one of the array of analog circuit blocks is coupled to at least one of the array of digital circuit blocks through the programmable interconnect to provide at least one mixed-signal function. 
     
     
         27 . The mixed-signal array of  claim 23 , wherein at least one of the array of analog circuit blocks is configurable to perform a first function in a first configuration and a second function in a second configuration.