Image sensor for improving linearity of analog-to-digital converter and image processing system including the same

Abstract

An image sensor and an image processing system including the same are provided. The image sensor includes a pixel array including a plurality of pixels each connected to one of first through m-th column lines to output a pixel signal, where “m” is an integer of at least 2; analog-to-digital converters each configured to receive the pixel signal corresponding to one of the first through m-th column lines, to compare the pixel signal with a ramp signal, and to convert the pixel signal to a digital pixel signal; and a blocking circuit connected to an input terminal of at least one of the analog-to-digital converters to block an influence of an operation of others among the analog-to-digital converters.

1 - 19 . (canceled) 
     
     
         20 . An image sensor comprising:
 a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal;   a plurality of analog-to-digital converters (ADCs) including a first group of ADCs and a second group of ADCs, the first group of ADCs including a first ADC and a second ADC, the second group of ADCs including a third ADC and a fourth ADC, each of the plurality of ADCs being configured to convert the pixel signal to a digital signal; and   a blocking circuit including a first buffer connected to the first ADC, a second buffer connected to the second ADC, a third buffer connected to the third ADC and a fourth buffer connected to the fourth ADC,   wherein each of the first buffer, the second buffer, the third buffer and the fourth buffer includes a current source and a transistor connected to the current source.   
     
     
         21 . The imager sensor of  claim 20 , wherein the current source is connected to a power supply voltage. 
     
     
         22 . The imager sensor of  claim 20 , wherein the current source is connected to a ground. 
     
     
         23 . The imager sensor of  claim 20 , wherein the transistor is a PMOS transistor. 
     
     
         24 . The imager sensor of  claim 20 , wherein the transistor is an NMOS transistor. 
     
     
         25 . The imager sensor of  claim 20 , further comprising a ramp signal generator configured to generate a ramp signal and output the ramp signal to the plurality of ADCs. 
     
     
         26 . The imager sensor of  claim 25 , wherein the ramp signal generator includes a ramp signal buffer configured to buffer and output the ramp signal. 
     
     
         27 . The imager sensor of  claim 25 , wherein each of the plurality of ADCs includes:
 a comparator configured to compare the pixel signal with the ramp signal to generate a comparison signal; and   a counter configured to generate the digital signal based on the comparison signal.   
     
     
         28 . The imager sensor of  claim 20 , wherein the first group of ADCs and the second group of ADCs are arranged in parallel. 
     
     
         29 . An image sensor comprising:
 a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal;   a plurality of analog-to-digital converters (ADCs) including a first group of ADCs and a second group of ADCs, the first group of ADCs including a first ADC and a second ADC, the second group of ADCs including a third ADC and a fourth ADC, each of the plurality of analog-to-digital converters being configured to convert the pixel signal to a digital signal;   a first buffer connected to the first ADC;   a second buffer connected to the second ADC;   a third buffer connected to the third ADC; and   a fourth buffer connected to the fourth ADC.   
     
     
         30 . The imager sensor of  claim 29 , wherein each of the first buffer, the second buffer, the third buffer and the fourth buffer includes a current source and a transistor connected to the current source. 
     
     
         31 . The imager sensor of  claim 29 , wherein the first group of ADCs and the second group of ADCs are arranged in parallel. 
     
     
         32 . The imager sensor of  claim 29 , further comprising a plurality of memories, each of the plurality of memories being configured to store the digital signal. 
     
     
         33 . The imager sensor of  claim 29 , further comprising a ramp signal generator configured to generate a ramp signal and output the ramp signal to the plurality of ADCs, the ramp signal generator including a ramp signal buffer configured to buffer and output the ramp signal. 
     
     
         34 . The imager sensor of  claim 29 , wherein each of the plurality of ADCs includes:
 a comparator configured to compare the pixel signal with a ramp signal to generate a comparison signal; and   a counter configured to generate the digital signal based on the comparison signal.   
     
     
         35 . An image sensor comprising:
 a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal;   a plurality of analog-to-digital converters (ADCs) including a first ADC, a second ADC, a third ADC and a fourth ADC, each of the plurality of analog-to-digital converters being configured to convert the pixel signal to a digital signal; and   a blocking circuit including a plurality of buffers that include a first buffer and a second buffer,   wherein the first buffer is connected to the first ADC and the second ADC, and   the second buffer is connected to the third ADC and the fourth ADC.   
     
     
         36 . The imager sensor of  claim 35 , further comprising a ramp signal generator configured to generate a ramp signal and output the ramp signal to the plurality of ADCs. 
     
     
         37 . The imager sensor of  claim 35 , wherein each of the first buffer and the second buffer includes a current source and a transistor connected to the current source. 
     
     
         38 . The imager sensor of  claim 35 , further comprising a capacitance connected between the first buffer and the first ADC. 
     
     
         39 . The imager sensor of  claim 35 , wherein each of the plurality of ADCs includes:
 a comparator configured to generate a comparison signal using the pixel signal; and   a counter configured to generate the digital signal using the comparison signal.