Cam memory cell

Abstract

A CAM memory cell including: a latch including N first TFETs serially connected one to the other between two supply electric potentials such that each source and drain of each first TFETs is connected either to one supply electric potentials or to the source or drain of another first TFETs, and wherein one electric potentials is applied on the gate of each first TFETs which are in reverse bias VDS and forward bias VGS, with N≥2; an output block connected to N−1 storage nodes formed at connection points between the first TFETs, and configured to read a data stored in the storage nodes and/or to output a value representative of a matching or mismatching between a search data and the stored data; a write block configured to apply a data to be stored in the storage nodes.

1 - 11 . (canceled) 
     
     
         12 : A CAM memory cell comprising:
 a latch comprising N first TFETs serially connected one to the other between two supply electric potentials such that each of source and drain of each of the N first TFETs is connected either to one of the two supply electric potentials or to the source or the drain of another one of the N first TFETs, and wherein at least one of the two supply electric potentials is applied on a gate of each of the N first TFETs such that the N first TFETs are in reverse bias V DS  and in forward bias V GS , with N≥2;   an output block connected to N−1 storage nodes formed at connection points between the N first TFETs, and configured to read a data stored in the N−1 storage nodes and/or to output a value representative of a matching or of a mismatching between a search data and the data stored in the N−1 storage nodes;   a write block configured to apply a data to be stored in the N−1 storage nodes.   
     
     
         13 : The CAM memory cell according to  claim 12 , wherein:
 the write block comprises N−1 MOSFETs and at least one first data line in which the data to be stored in at least one of the N−1 storage nodes is able to be applied;   each one of the N−1 MOSFETs has one of its source or drain connected to the at least one of the N−1 storage nodes and the other one of its source or drain connected to the first data line.   
     
     
         14 : The CAM memory cell according to  claim 13 , wherein the write block comprises N−1 first data lines such that each one of the N−1 first data line is connected to one of the N−1 MOSFETs. 
     
     
         15 : The CAM memory cell according to  claim 13 , wherein the gate of each of the N−1 MOSFETs is connected to a write word line in which a write control signal is able to be applied. 
     
     
         16 : The CAM memory cell according to  claim 15 , wherein:
 the write block comprises at least two first data lines;   a first one of the N−1 MOSFETs is a n-MOSFET having one of its source or drain connected to a first one of the two first data lines and the other one of its source or drain connected to a first one of the N−1 storage nodes;   a second one of the N−1 MOSFETs is a n-MOSFET having one of its source or drain connected to a second one of the two first data lines and the other one of its source or drain connected to a second one of the N−1 storage nodes.   
     
     
         17 : The CAM memory cell according to  claim 12 , wherein the output block comprises one or plural second TFETs each having its gate connected to one of the N−1 storage nodes, one of its source or drain connected to a match line and the other one of its source or drain connected to a second data line in which the search data is able to be applied, and wherein an electric potential of the match line is able to discharge when the search data does not correspond to the data stored in the N−1 storage nodes. 
     
     
         18 : The CAM memory cell according to  claim 17 , wherein:
 the output block comprises at least two second data lines;   a first one of the second TFETs is a n-TFET having its drain connected to the match line and its source connected to a first one of the two second data lines;   a second one of the second TFETs is a p-TFET having its source connected to the match line and its drain connected to a second one of the two second data lines;   the gates of the first one and second one of the second TFETs are connected to the same storage node or to two different storage nodes.   
     
     
         19 : The CAM memory cell according to  claim 12 , wherein:
 the write block comprises at least two first data lines;   the output block comprises at least two second data lines;   the first and second data lines are same data lines.   
     
     
         20 : The CAM memory cell according to  claim 12 , wherein the output block comprises one or plural second TFETs each having its gate connected to one of the N−1 storage nodes, one of its source or drain connected to a read bit line and the other of its source or drain connected to a read word line in which a read triggering signal is to be applied, and wherein an electric potential of the read bit line is able to discharge or not according to the value stored in said one of the N−1 storage nodes. 
     
     
         21 : The CAM memory cell according to  claim 12 , wherein N=3 and the CAM memory cell forms a TCAM. 
     
     
         22 : CAM memory array comprising plural CAM memory cells according to  claim 12 , wherein the CAM memory cells are arranged according to an array of rows and columns.