Predictive memory maintenance

Abstract

Predictive memory maintenance in accordance with one aspect of the present description, can anticipate a failure of a selected primary memory die of an array, and pre-load a spare memory die with the data of the selected primary memory die deemed to have a likelihood of failure, prior to any actual failure of the selected memory die. In the event that the selected primary memory die does subsequently fail, the spare memory die pre-loaded with the data of the selected primary memory die can readily take the place of the failed primary memory die with a pre-existing copy of the data of the failed primary memory die. Other aspects are described herein.

1 - 23 . (canceled) 
     
     
         24 . An apparatus comprising:
 error correction code (ECC) logic to detect an error rate for a memory die; and   logic to:
 determine that the error rate of the memory die is indicative of future failure, and 
 prior to failure, copy data from the memory die with the error rate indicative of future failure to spare space; 
   wherein memory accesses to the memory die continue after the memory die is determined to have the error rate indicative of future failure but before failure of the memory die.   
     
     
         25 . The apparatus of  claim 24 , wherein:
 the spare space includes a spare memory die.   
     
     
         26 . The apparatus of  claim 24 , wherein:
 the logic is to: during a regular data transfer, cause data to be stored on both the memory die and the spare space.   
     
     
         27 . The apparatus of  claim 24 , wherein:
 the logic is to: cause any data updates to be transferred in parallel to the memory die and the spare space.   
     
     
         28 . The apparatus of  claim 24 , wherein:
 the logic is to: cause any data updates to the memory die to be copied from the memory die to the spare space.   
     
     
         29 . The apparatus of  claim 24 , wherein:
 the logic is to:
 after the determination that the error rate of the memory die is indicative of future failure, determine that another memory die's error rate is more indicative of future failure; and 
 prior to failure of the other memory die, copy data from the other memory die to the spare space. 
   
     
     
         30 . The apparatus of  claim 24 , wherein:
 if the ECC logic fails to correct an error from an operation to read data, access the data from the spare space.   
     
     
         31 . The apparatus of  claim 24 , wherein:
 the apparatus comprises a memory controller.   
     
     
         32 . The apparatus of  claim 24 , wherein:
 the error rate includes a raw bit error rate (RBER).   
     
     
         33 . The apparatus of  claim 24 , wherein:
 the logic is to further: disable the memory die after failure.   
     
     
         34 . A memory controller comprising:
 logic to:
 determine that a memory die has a performance characteristic indicative of future failure, 
 select the memory die for potential replacement, and 
 prior to failure, copy data from the memory die with the performance characteristic indicative of future failure to spare space; 
   wherein memory accesses to the memory die continue after the memory die is determined to have the performance characteristic indicative of failure but before failure of the memory die.   
     
     
         35 . The memory controller of  claim 34 , wherein:
 the performance characteristic includes an error rate.   
     
     
         36 . The memory controller of  claim 34 , wherein:
 the performance characteristic includes a temperature of the die.   
     
     
         37 . The memory controller of  claim 34 , wherein:
 the spare space includes a spare memory die.   
     
     
         38 . The memory controller of  claim 34 , wherein:
 the logic is to: during a regular data transfer, cause data to be stored on both the memory die and the spare space.   
     
     
         39 . The memory controller of  claim 34 , wherein:
 the logic is to: cause any data updates to be transferred in parallel to the memory die and the spare space.   
     
     
         40 . The memory controller of  claim 34 , wherein:
 the logic is to: cause any data updates to the memory die to be copied from the memory die to the spare space.   
     
     
         41 . A system comprising:
 a memory device including a memory die;   a memory controller including:
 logic to: 
 determine that the memory die has a performance characteristic indicative of future failure, 
 select the memory die for potential replacement, and 
 prior to failure, copy data from the memory die with the performance characteristic indicative of future failure to spare space; 
   wherein memory accesses to the memory die continue after the memory die is determined to have the performance characteristic indicative of failure but before failure of the memory die.   
     
     
         42 . The system of  claim 41 , wherein:
 the memory die is disposed on dual in line memory module (DIMM).   
     
     
         43 . The system of  claim 41 , wherein:
 the memory device includes one or more of three-dimensional (3D) crosspoint memory, resistive memory, and NAND flash memory.   
     
     
         44 . The system of  claim 41 , wherein:
 the memory device includes a temperature sensor; and   wherein the performance characteristic is a temperature of the memory die.   
     
     
         45 . The system of  claim 41 , wherein:
 the performance characteristic includes an error rate.   
     
     
         46 . The system of  claim 41 , further comprising one or more of:
 a processor, a network adaptor, and a video controller.