Nested wrap-around memory access

Abstract

A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

1 . A device configured to execute an access operation, comprising:
 logic responsive to a command specifying a supplied starting address to generate an address sequence for a block of memory, the block including a number N of sections having a number M of addressable units, the numbers N and M being integers greater than one, wherein the supplied starting address identifies a starting section with a non-zero address offset from a lower boundary of the block, and has a second non-zero address offset from a lower boundary of the starting section;   the address sequence including the number N of address sub-sequences, including a starting sub-sequence for the starting section, and a series of sub-sequences incrementing by section to a section which includes an upper boundary of the block, and wrapping around to a section at the lower boundary of the block; and   the sub-sequences for corresponding sections of the block having respective starting addresses having the second non-zero address offset from respective lower boundaries of the corresponding sections, and addresses incrementing by an addressable unit from the respective starting addresses to an upper boundary of the corresponding section, and wrapping around to a lower boundary of the corresponding section.   
     
     
         2 . The device of  claim 1 , including a parameter store holding:
 a first parameter specifying a section length equal to the number M of addressable units; and   a second parameter specifying a wrap-around count equal to the number N of address sub-sequences.   
     
     
         3 . The device of  claim 2  wherein the parameter store is non-volatile memory. 
     
     
         4 . The device of  claim 2  wherein the parameter store is write-once memory. 
     
     
         5 . The device of  claim 1  wherein one or both of the numbers N and M comprise a command parameter. 
     
     
         6 . The device of  claim 1 , wherein the logic includes an address sequencer to generate the address sequence by setting a wrap starting address to the supplied starting address, and
 a) for a sub-sequence in the N address sub-sequences of a given section, beginning with the wrap starting address, incrementing by the addressable unit until an upper boundary of the given section, wrapping around to a lower boundary of the given section, and incrementing to an address preceding the wrap starting address,   b) if the wrap starting address plus the number M is less than the upper boundary of the block, then incrementing the wrap starting address by the number M, else setting the wrap starting address to the lower boundary of the block plus an address offset identified by the supplied starting address, and   c) repeating steps a) and b) until a termination event.   
     
     
         7 . The device of  claim 6  wherein the lower boundaries and upper boundaries of sections in the N sections of the block have addresses in which members of a first set of least significant bits are all zero or are all one, respectively. 
     
     
         8 . The device of  claim 7  wherein the lower boundary and upper boundary of the block have addresses in which members of a second set of least significant bits are all zero or are all one, respectively. 
     
     
         9 . An access operation configured to be executed by a device, the access operation comprising:
 receiving a command specifying a supplied starting address, where the supplied starting address has a non-zero address offset from a lower boundary of a wrap-around address section; and   generating an address sequence for a block of memory, the address sequence including a number N of address sub-sequences, including a starting sub-sequence for a starting section of the block identified by the supplied starting address, and a series of sub-sequences incrementing by section to a section which includes an upper boundary of the block, wrapping around to a section at a lower boundary of the block, and   each sub-sequence of a given section having a number M of addresses, including a starting address having the non-zero address offset from a lower boundary of the given section, and a series of addresses incrementing by an addressable unit from the starting address of the given section to an upper boundary of the given section, wrapping around to the lower boundary of the given section.   
     
     
         10 . The operation of  claim 9 , wherein said generating an address sequence for a block of memory includes, executing a process using a first parameter specifying a section length equal to the number M, and a second parameter specifying a wrap-around count equal to the number N, the first parameter and the second parameter held in a parameter store, the block having a lower boundary and an upper boundary, and including, after setting a starting address to the supplied starting address:
 a) generating an address sub-sequence of the N address sub-sequences beginning with the starting address, incrementing by an addressable unit until an upper boundary of the section, wrapping around to a lower boundary of section, and incrementing until an address of an addressable unit immediately precedes the starting address,   b) if the starting address plus the section length is less than the upper boundary of the block, then incrementing the starting address by the section length, else setting the starting address to the lower boundary of the block plus an address offset identified by the supplied starting address, and   c) repeating steps a) and b) until a termination event.   
     
     
         11 . The operation of  claim 10  wherein the termination event is receipt of a control signal. 
     
     
         12 . The operation of  claim 10  wherein the lower boundaries and upper boundaries of the address sections have addresses in which members of a first set of least significant bits are all zero or are all one, respectively. 
     
     
         13 . The operation of  claim 12  wherein the lower boundary and upper boundary of the block have addresses in which members of a second set of least significant bits are all zero or are all one, respectively. 
     
     
         14 . The operation of  claim 9  wherein the block is an entire addressable space of a memory on the device. 
     
     
         15 . The operation of  claim 10  wherein at least one of the section length and wrap-around count is stored in non-volatile memory. 
     
     
         16 . The operation of  claim 9  wherein the access operation is a read operation. 
     
     
         17 . The operation of  claim 9  wherein the access operation is a write operation. 
     
     
         18 . The operation of  claim 9  storing parameters specifying the numbers M and N in a write-once memory. 
     
     
         19 . A method for wrap-around addressing, comprising:
 using a starting address, a wrap-around section length and a wrap-around block length;   a) in a current wrap-around section identified by the starting address, the current wrap-around section being in a wrap-around block having the wrap-around block length, generating a set of addresses addressing the current wrap-around section in a wrap-around manner;   b) proceeding in a wrap-around manner to a next section within said wrap-around block, and   c) repeating steps a) and b), until a termination event,   wherein the wrap-around section length is equal to a number of addresses in the set of addresses in the current wrap-around section, and the wrap-around block length is equal to a number of wrap-around sections in the wrap-around block.   
     
     
         20 . The method of  claim 19 , including storing a wrap-around section length parameter and a wrap-around count parameter, wherein the wrap-around section length is determined using the wrap-around section length parameter and the wrap-around block length is determined using the wrap-around section length parameter and the wrap-around count parameter.