Nanowire device with reduced parasitics

Abstract

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

We claim: 
     
         1 . A method of manufacturing a nanowire transistor, comprising:
 oxidizing a well implant to form a local isolation region;   forming a fin on the local isolation region that includes alternating layers of a first semiconductor and a second semiconductor, wherein an initial layer of the first semiconductor abuts the local isolation region, and wherein the fin extends from a first extension region to a second extension region;   implanting an etch stop dopant in the first extension region and in the second extension region;   forming a dummy gate opening to expose a gate region of the fin; and   selectively etching the layers of the first semiconductor in the gate region of the fin to form nanowires from the layers of the second semiconductor in the gate region, wherein the implanted etch stop dopant inhibits a selective etching of the layers of the first semiconductor in the first extension region and in the second extension region.   
     
     
         2 . The method of  claim 1 , further comprising:
 selectively oxidizing the layers of the first semiconductor such that each layer of the first semiconductor includes oxidized caps extending from the dummy gate opening into the first extension region and into the second extension region; and   forming a replacement metal gate around the nanowires.   
     
     
         3 . The method of  claim 1 , wherein the first semiconductor is silicon and the second semiconductor is silicon germanium. 
     
     
         4 . The method of  claim 1 , wherein the first semiconductor is silicon germanium and the second semiconductor is silicon. 
     
     
         5 . The method of  claim 4 , wherein implanting the etch stop dopant comprises implanting carbon. 
     
     
         6 . The method of  claim 2 , wherein depositing the replacement metal gate comprises depositing an initial high-k dielectric layer. 
     
     
         7 . The method of  claim 6 , wherein depositing the replacement metal gate further comprises depositing a subsequent work function layer. 
     
     
         8 . The method of  claim 7 , wherein depositing the replacement metal gate further comprises depositing a metal gate fill. 
     
     
         9 . The method of  claim 1 , wherein forming the fin comprises depositing the initial layer of the first semiconductor, a second layer of the second semiconductor, a third layer of the first semiconductor, and a fourth layer of the second semiconductor. 
     
     
         10 . The method of  claim 1 , wherein forming the fin comprises a selective isolation trench process.