VARYING ENERGY BARRIERS OF MAGNETIC TUNNEL JUNCTIONS (MTJs) IN DIFFERENT MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) ARRAYS IN A SEMICONDUCTOR DIE TO FACILITATE USE OF MRAM FOR DIFFERENT MEMORY APPLICATIONS

Abstract

Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

1 . A semiconductor die, comprising:
 a first magnetic tunnel junction (MTJ) stack, comprising:
 a first pinned layer having a first pinned layer magnetic moment; 
 a first free layer having a first free layer magnetic moment; and 
 a first tunnel barrier layer disposed between the first pinned layer and the first free layer, wherein the first MTJ stack has a first energy barrier; and 
   a second MTJ stack, comprising:
 a second pinned layer having a second pinned layer magnetic moment; 
 a second free layer having a second free layer magnetic moment; and 
 a second tunnel barrier layer disposed between the second pinned layer and the second free layer, wherein the second MTJ stack has a second energy barrier different from the first energy barrier. 
   
     
     
         2 . The semiconductor die of  claim 1 , wherein:
 the first energy barrier of the first MTJ stack is an amount of energy to substantially invert a direction of the first free layer magnetic moment in the first free layer; and   the second energy barrier of the second MTJ stack is an amount of energy to substantially invert a direction of the second free layer magnetic moment in the second free layer.   
     
     
         3 . The semiconductor die of  claim 2 , wherein:
 the first pinned layer further comprises a first material; and   the second pinned layer further comprises a second material different from the first material of the first pinned layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         4 . The semiconductor die of  claim 3 , wherein:
 the first material of the first pinned layer comprises one or more of Cobalt (Co), Platinum (Pt), and Nickel (Ni); and   the second material of the second pinned layer comprises one of more of Co, Pt, and Ni.   
     
     
         5 . The semiconductor die of  claim 2 , wherein:
 the first free layer further comprises a first material; and   the second free layer further comprises a second material different from the first material of the first free layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         6 . The semiconductor die of  claim 5 , wherein:
 the first material of the first free layer comprises one or more of Cobalt (Co), Iron (Fe), and Boron (B) such that the first free layer has a first effective anisotropy energy constant; and   the second material of the second free layer comprises one or more of Co, Fe, and B such that the second free layer has a second effective anisotropy energy constant less than the first effective anisotropy energy constant.   
     
     
         7 . The semiconductor die of  claim 2 , wherein:
 the first tunnel barrier layer further comprises a first material; and   the second tunnel barrier layer further comprises a second material different from the first material of the first tunnel barrier layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         8 . The semiconductor die of  claim 2 , wherein:
 the first pinned layer further comprises a first width; and   the second pinned layer further comprises a second width different from the first width of the first pinned layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         9 . The semiconductor die of  claim 2 , wherein:
 the first free layer further comprises a first width; and   the second free layer further comprises a second width different from the first width of the first free layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         10 . The semiconductor die of  claim 9 , wherein:
 the first width of the first free layer comprises a width less than thirty-five (35) nanometers (nm), between thirty-five (35) nm and seventy (70) nm, or greater than seventy (70) nm; and   the second width of the second free layer comprises a width less than thirty-five (35) nm, between thirty-five (35) nm and seventy (70) nm, or greater than seventy (70) nm.   
     
     
         11 . The semiconductor die of  claim 2 , wherein:
 the first tunnel barrier layer further comprises a first width; and   the second tunnel barrier layer further comprises a second width different from the first width of the first tunnel barrier layer such that the second energy barrier of the second MTJ stack is different from the first energy barrier of the first MTJ stack.   
     
     
         12 . The semiconductor die of  claim 11 , wherein:
 the first width of the first tunnel barrier layer is associated with a first resistance area product of the first tunnel barrier layer such that the first resistance area product comprises a resistance area product of less than five (5) ohm-micrometers squared (Ωμm 2 ), between five (5) and eight (8) Ωμm 2 , or between eight (8) and ten (10) Ωμm 2 ; and   the second width of the second tunnel barrier layer is associated with a second resistance area product of the second tunnel barrier layer such that the second resistance area product comprises a resistance area product of less than five (5) Ωμm 2 , between five (5) and eight (8) Ωμm 2 , or between eight (8) and ten (10) Ωμm 2 .   
     
     
         13 . The semiconductor die of  claim 1 , further comprising:
 a third MTJ stack, comprising:
 a third pinned layer having a third pinned layer magnetic moment; 
 a third free layer having a third free layer magnetic moment; and 
 a third tunnel barrier layer disposed between the third pinned layer and the third free layer, wherein the third MTJ stack has a third energy barrier different from the first energy barrier and the second energy barrier. 
   
     
     
         14 . The semiconductor die of  claim 1 , further comprising:
 a first magneto-resistive random access memory (MRAM) bit cell of a first MRAM array, comprising:
 a first MTJ comprising a first top electrode layer and a first bottom electrode layer, wherein the first MTJ stack is disposed between the first top electrode layer and the first bottom electrode layer; and 
 a first access transistor comprising a first gate, a first source, and a first drain, the first access transistor coupled to the first MTJ; and 
   a second MRAM bit cell of a second MRAM array, comprising:
 a second MTJ comprising a second top electrode layer and a second bottom electrode layer, wherein the second MTJ stack is disposed between the second top electrode layer and the second bottom electrode layer; and 
 a second access transistor comprising a second gate, a second source, and a second drain, the second access transistor coupled to the second MTJ. 
   
     
     
         15 . The semiconductor die of  claim 14 , wherein the first MTJ of the first MRAM bit cell of the first MRAM array and the second MTJ of the second MRAM bit cell of the second MRAM array are in a same layer of the semiconductor die. 
     
     
         16 . The semiconductor die of  claim 14 , wherein:
 the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;   the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded static random access memory (eSRAM); and   the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in embedded dynamic random access memory (eDRAM).   
     
     
         17 . The semiconductor die of  claim 14 , wherein:
 the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;   the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded static random access memory (eSRAM); and   the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in eFlash memory.   
     
     
         18 . The semiconductor die of  claim 14 , wherein:
 the first energy barrier of the first MTJ stack is lower than the second energy barrier of the second MTJ stack;   the first MRAM bit cell of the first MRAM array is configured as an MRAM bit cell in embedded dynamic random access memory (eDRAM); and   the second MRAM bit cell of the second MRAM array is configured as an MRAM bit cell in eFlash memory.   
     
     
         19 . The semiconductor die of  claim 1  integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. 
     
     
         20 . A semiconductor die, comprising:
 a first means for storing data, comprising:
 a first means for storing a fixed magnetic moment having a first fixed magnetic moment; 
 a first means for storing a programmable magnetic moment having a first programmable magnetic moment; and 
 a first means for transferring spin polarization of electrons disposed between the first means for storing the fixed magnetic moment and the first means for storing the programmable magnetic moment, wherein the first means for storing data has a first energy barrier; and 
   a second means for storing data, comprising:
 a second means for storing a fixed magnetic moment having a second fixed magnetic moment; 
 a second means for storing a programmable magnetic moment having a second programmable magnetic moment; and 
 a second means for transferring spin polarization of electrons disposed between the second means for storing the fixed magnetic moment and the second means for storing the programmable magnetic moment, wherein the second means for storing data has a second energy barrier different from the first energy barrier. 
   
     
     
         21 . A method of varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die, comprising:
 forming a first blocking layer over a second via of a second MRAM array, wherein the second via is in an interconnect layer of the semiconductor die;   depositing a first MTJ stack film over a first via of a first MRAM array and at least a portion of the first blocking layer, wherein the first via is in the interconnect layer of the semiconductor die;   depositing a first top electrode film over the first MTJ stack film;   depositing a first mask over a portion of the first top electrode film over the first MTJ stack film over the first via;   removing a portion of the first top electrode film and a portion of the first MTJ stack film not under the first mask to form a first top electrode layer over a first MTJ stack over the first via of the first MRAM array;   removing at least a portion of the first blocking layer over the second via of the second MRAM array;   depositing a second MTJ stack film over the second via of the second MRAM array;   depositing a second top electrode film over the second MTJ stack film;   depositing a second mask over a portion of the second top electrode film over the second MTJ stack film over the second via; and   removing a portion of the second top electrode film and a portion of the second MTJ stack film not under the second mask to form a second top electrode layer over a second MTJ stack over the second via of the second MRAM array.   
     
     
         22 . The method of  claim 21 , further comprising:
 removing the first mask; and   forming a second blocking layer over the first MTJ stack of the first MRAM array, wherein:
 depositing the second MTJ stack film over the second via of the second MRAM array comprises depositing the second MTJ stack film over the second via of the second MRAM array and at least a portion of the second blocking layer. 
   
     
     
         23 . The method of  claim 22 , wherein:
 depositing the first MTJ stack film over the first via of the first MRAM array and at least the portion of the first blocking layer comprises depositing a first pinned film, a first tunnel barrier film, and a first free film over the first via of the first MRAM array and at least the portion of the first blocking layer; and   depositing the second MTJ stack film over the second via of the second MRAM array and at least the portion of the second blocking layer comprises depositing a second pinned film, a second tunnel barrier film, and a second free film over the second via of the second MRAM array and at least the portion of the second blocking layer, wherein the interconnect layer further comprises a bottom electrode film over the first via of the first MRAM array and the second via of the second MRAM array.   
     
     
         24 . The method of  claim 22 , wherein:
 depositing the first MTJ stack film over the first via of the first MRAM array and at least the portion of the first blocking layer comprises depositing a first bottom electrode film, a first pinned film, a first tunnel barrier film, and a first free film over the first via of the first MRAM array and at least the portion of the first blocking layer; and   depositing the second MTJ stack film over the second via of the second MRAM array and at least the portion of the second blocking layer comprises depositing a second bottom electrode film, a second pinned film, a second tunnel barrier film, and a second free film over the second via of the second MRAM array and at least the portion of the second blocking layer.   
     
     
         25 . The method of  claim 23 , further comprising:
 removing a portion of the bottom electrode film not under the first MTJ stack and the second MTJ stack to form a first bottom electrode layer under the first MTJ stack and a second bottom electrode layer under the second MTJ stack.   
     
     
         26 . The method of  claim 25 , further comprising:
 forming a spacer film adjacent to the first MTJ stack and the second MTJ stack;   depositing a dielectric layer adjacent to the spacer film and over the first MTJ stack and the second MTJ stack;   removing a portion of the dielectric layer over the first MTJ stack and the second MTJ stack to expose a first top surface of the first top electrode layer and a second top surface of the second top electrode layer;   forming a first top electrode via over the first top surface of the first top electrode layer; and   forming a second top electrode via over the second top surface of the second top electrode layer.   
     
     
         27 . The method of  claim 26 , wherein forming the spacer film adjacent to the first MTJ stack and the second MTJ stack comprises forming the spacer film adjacent to the first MTJ stack and the second MTJ stack to expose a top surface of the interconnect layer of the semiconductor die. 
     
     
         28 . The method of  claim 22 , further comprising:
 forming the first blocking layer over a third via of a third MRAM array, wherein the third via is in the interconnect layer of the semiconductor die;   removing at least a portion of the first blocking layer over the third via of the third MRAM array;   forming the second blocking layer over a third MTJ stack of the third MRAM array;   removing at least a portion of the second blocking layer over the third via of the third MRAM array;   depositing a third MTJ stack film over the third via of the third MRAM array;   depositing a third top electrode film over the third MTJ stack film;   depositing a third mask over a portion of the third top electrode film over the third MTJ stack film over the third via; and   removing a portion of the third top electrode film and a portion of the third MTJ stack film not under the third mask to form a third top electrode layer over the third MTJ stack over the third via of the third MRAM array.   
     
     
         29 . A central processing unit (CPU) system, comprising:
 a system bus;   at least one CPU core communicatively coupled to the system bus;   a memory controller communicatively coupled to the system bus; and   a memory system communicatively coupled to the system bus, comprising:
 a first magneto-resistive random access memory (MRAM) bit cell of a first MRAM array, comprising:
 a first magnetic tunnel junction (MTJ) stack, comprising: 
 a first pinned layer having a first pinned layer magnetic moment; 
 a first free layer having a first free layer magnetic moment; and 
 
   a first tunnel barrier layer disposed between the first pinned layer and the first free layer, wherein the first MTJ stack has a first energy barrier;
 a first MTJ comprising a first top electrode layer and a first bottom electrode layer, wherein the first MTJ stack is disposed between the first top electrode layer and the first bottom electrode layer; and 
 a first access transistor comprising a first gate, a first source, and a first drain, the first access transistor coupled to the first MTJ; and 
   a second MRAM bit cell of a second MRAM array, comprising:
 a second MTJ stack, comprising:
 a second pinned layer having a second pinned layer magnetic moment; 
 a second free layer having a second free layer magnetic moment; and 
 a second tunnel barrier layer disposed between the second pinned layer and the second free layer, wherein the second MTJ stack has a second energy barrier different from the first energy barrier; 
 
 a second MTJ comprising a second top electrode layer and a second bottom electrode layer, wherein the second MTJ stack is disposed between the second top electrode layer and the second bottom electrode layer; and 
 a second access transistor comprising a second gate, a second source, and a second drain, the second access transistor coupled to the second MTJ.