Multi-source address translation service (ats) with a single ats resource

Abstract

Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.

1 . (canceled) 
     
     
         2 . A processor comprising:
 an input-output memory management unit (IOMMU) circuit; and   an address translator circuit coupled to the IOMMU circuit and a first functional unit of the processor, wherein the address translator circuit is to:
 receive a first transaction with a first memory address and an indicator that identifies the first transaction as a head of a burst of transactions; 
 send the first memory address of the first transaction to the IOMMU circuit to be translated; 
 receive a first translated memory address from the IOMMU circuit; 
 store the first translated memory address; 
 dispatch the first transaction with the first translated address to a memory device; 
 receive a second transaction with a second memory address and an indicator that identifies the second transaction as one of the burst of transactions; 
 replace the second memory address of the second transaction with the first translated memory address; and 
 dispatch the second transaction with the first translated address to the memory device. 
   
     
     
         3 . The processor of  claim 2 , further comprising:
 a second address translator circuit coupled to the IOMMU circuit and a second functional unit of the processor; and   an arbiter circuit coupled to the IOMMU circuit, the address translator circuit, and the second address translator circuit.   
     
     
         4 . The processor of  claim 3 , further comprising a second arbiter circuit coupled to the address translator circuit, the second address translator circuit, and the memory device. 
     
     
         5 . The processor of  claim 2 , further comprising:
 a second address translator circuit coupled to the IOMMU circuit and a second functional unit of the processor, wherein the second address translator circuit is to:
 receive a third transaction with a third memory address and an indicator that identifies the third transaction as a head of a second burst of transactions; 
 send the third memory address of the third transaction to the IOMMU circuit to be translated; 
 receive a second translated memory address from the IOMMU circuit; 
 store the second translated memory address; 
 dispatch the third transaction with the second translated address to the memory device; 
 receive a fourth transaction with a fourth memory address and an indicator that identifies the fourth transaction as one of the second burst of transactions; 
 replace the fourth memory address of the fourth transaction with the second translated memory address; and 
 dispatch the fourth transaction with the second translated address to the memory device. 
   
     
     
         6 . The processor of  claim 2 , wherein IOMMU circuit is to:
 receive a translation request from the address translator circuit, the translation request comprising the first memory address;   translate the first memory address to the first translated address; and   send a translation response to the address translator circuit, the translation response comprising the first translated address.   
     
     
         7 . The processor of  claim 2 , further comprising:
 a second address translator circuit coupled to the IOMMU circuit and a second functional unit of the processor, and wherein IOMMU circuit is to:
 receive a translation request from the address translator circuit, the translation request comprising the first memory address; 
 translate the first memory address to the first translated address; 
 send a translation response to the address translator circuit, the translation response comprising the first translated address; 
 receive a second translation request from the second address translator circuit, the second translation request comprising a second memory address; 
 translate the second memory address to a second translated address; and 
 send a second translation response to the second address translator circuit, the second translation response comprising the second translated address. 
   
     
     
         8 . The processor of  claim 2 , wherein the address translator circuit is to:
 check whether an indicator of a current transaction identifies a head of a burst of transactions or one of the burst of transactions;   when the indicator of the current transaction identifies the head of the burst of transactions,
 send a translation request with the current transaction to the IOMMU circuit to translate a current memory address to a current translated address, 
 receive a translation response with the current translated address, and 
 store the current translated address associated with the head of the burst of transactions; and 
   when the indicator of the current transaction identifies one of the burst of transactions, replace the current memory address with the current translated address.   
     
     
         9 . The processor of  claim 2 , wherein the address translator circuit comprises a cache to store the first memory address and the first translated memory address. 
     
     
         10 . The processor of  claim 2 , further comprising:
 a second address translator circuit coupled to the IOMMU circuit and a second functional unit of the processor, wherein the address translator circuit comprises a first cache to store the first memory address and the first translated memory address, and wherein the second address translator circuit comprises a second cache to store a second memory address and a second translated memory address.   
     
     
         11 . The processor of  claim 2 , wherein the address translator circuit comprises a cache, wherein the address translator circuit is to:
 check whether the cache already stores a memory address and a translated address;   when already stored in the cache, substitute the memory address in a transaction with the translated address stored in the cache; and   when not already stored in the cache, generate a translation request to send to the IOMMU circuit to translate the memory address to the translated address.   
     
     
         12 . The processor of  claim 2 , further comprising:
 a second address translator circuit coupled to the IOMMU circuit and a second functional unit of the processor; and   an arbiter circuit coupled to the IOMMU circuit, the address translator circuit, and the second address translator circuit, wherein the arbiter circuit is to:
 receive a first translation request from the address translator circuit and a second translation request from the second address translator circuit; 
 determine a priority for the first translation request and the second translation request; and 
 dispatch the first translation request and the second translation request to the IOMMU circuit according to the priority. 
   
     
     
         13 . The processor of  claim 2 , wherein the indicator that identifies the second transaction as one of the burst of transactions is a burst notation that indicates that data associated with the burst of transactions is within an address boundary. 
     
     
         14 . The processor of  claim 2 , wherein the first memory address is a base address that corresponds to a memory page, wherein the first translated address is a physical memory address. 
     
     
         15 . A method comprising:
 receiving, at an address translator circuit of a processor, a first transaction with a first memory address and an indicator that identifies the first transaction as a head of a burst of transactions;   sending, by the address translator circuit to an input-output memory management unit (IOMMU) circuit of the processor, the first memory address of the first transaction to be translated;   receiving, at the address translator circuit, a first translated memory address from the IOMMU circuit;   storing the first translated memory address in a cache associated with the address translator circuit;   dispatching, by the address translator circuit, the first transaction with the first translated address to a memory device;   receiving, at the address translator circuit, a second transaction with a second memory address and an indicator that identifies the second transaction as one of the burst of transactions;   replacing, by the address translator circuit, the second memory address of the second transaction with the first translated memory address; and   dispatching the second transaction with the first translated address to the memory device.   
     
     
         16 . The method of  claim 15 , further comprising:
 associating, by the address translator circuit, the first translated address with the second transaction before dispatching the second transaction to the memory device.   
     
     
         17 . The method of  claim 15 , further comprising:
 associating, by the address translator circuit, the first translated address with the second transaction before dispatching the second transaction to the memory device.   
     
     
         18 . A system comprising:
 a memory device;   a processor coupled to the memory device, the processor comprising:
 an arbiter circuit operatively coupled to the memory device; 
 a first functional unit; 
 a second functional unit; 
 a memory management circuit; 
 a first address translator circuit coupled to the first functional unit, the memory management circuit, and the arbiter circuit; 
 a second address translator circuit coupled to the second functional unit, the memory management circuit, and the arbiter circuit, wherein the first address translator circuit is to:
 receive a first transaction with a first memory address and an indicator that identifies the first transaction as a head of a burst of transactions; 
 send the first memory address of the first transaction to the memory management circuit to be translated; 
 receive a first translated memory address from the memory management circuit; 
 store the first translated memory address; 
 dispatch the first transaction with the first translated address to the memory device via the arbiter circuit; 
 receive a second transaction with a second memory address and an indicator that identifies the second transaction as one of the burst of transactions; 
 replace the second memory address of the second transaction with the first translated memory address; and 
 dispatch the second transaction with the first translated address to the memory device via the arbiter circuit. 
 
   
     
     
         19 . The system of  claim 18 , wherein the second address translator circuit is to:
 receive a third transaction with a third memory address and an indicator that identifies the third transaction as a head of a second burst of transactions;   send the third memory address of the third transaction to the memory management circuit to be translated;   receive a second translated memory address from the memory management circuit;   store the second translated memory address;   dispatch the third transaction with the second translated address to the memory device;   receive a fourth transaction with a fourth memory address and an indicator that identifies the fourth transaction as one of the second burst of transactions;   replace the fourth memory address of the fourth transaction with the second translated memory address; and   dispatch the fourth transaction with the second translated address to the memory device.   
     
     
         20 . The system of  claim 18 , wherein the memory management circuit is to:
 receive a translation request from the first address translator circuit or the second address translator circuit, the translation request comprising an original memory address;   translate the original memory address to a translated address of the original memory address; and   send a translation response to the respective one of the first address translator circuit or the second address translator circuit, the translation response comprising the translated address of the original memory address.   
     
     
         21 . The system of  claim 18 , wherein the memory management circuit is to:
 receive a first translation request from the first address translator circuit, the first translation request comprising the first memory address;   translate the first memory address to the first translated address;   send a first translation response to the address translator circuit, the first translation response comprising the first translated address;   receive a second translation request from the second address translator circuit, the second translation request comprising a second memory address;   translate the second memory address to a second translated address; and   send a second translation response to the second address translator circuit, the second translation response comprising the second translated address.