Transaction identification synchronization

Abstract

Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.

What is claimed is: 
     
         1 . A memory module comprising:
 a memory controller;   an incremental counter to generate a transaction identification;   a parity generator to generate a parity bit from a combination of the transaction identification and command and data address bits; and   communication nodes to receive a host parity bit and the command and data address bits from a host to synchronize the transaction identification between the memory controller and the host.   
     
     
         2 . The memory module of  claim 1 , wherein the memory module includes a comparison module arranged to compare the generated transaction identification to a list of outstanding transaction identifications and to compare the generated parity bit to a running parity pattern. 
     
     
         3 . A communication method for communication with a host, the communication method comprising:
 receiving, in a memory module, a host parity bit and command and data address bits from the host;   generating, in the memory module, a transaction identification using an incremental counter;   generating, in the memory module using a parity generator, a parity bit from a combination of the transaction identification and the command and data address bits; and   synchronizing, via communication nodes using a memory controller of the memory module, the transaction identification between the memory controller and the host.   
     
     
         4 . The communication method of  claim 3 , wherein the communication method includes:
 comparing the generated transaction identification to a list of outstanding transaction identifications; and   comparing the generated parity bit to a running parity pattern.   
     
     
         5 . The communication method of  claim 3 , wherein the communication method includes:
 calculating an error-correcting code for data, corresponding to a read command, from a combination including the data, an operational code, and a message; and   transmitting the data including the error-correcting code from the memory controller to the host.   
     
     
         6 . A non-transitory computer-readable medium storing computer instructions that, when executed by one or more processors, cause performance of operations in a memory module, the operations comprising:
 receiving, in the memory module, a host parity bit and command and data address bits from a host;   generating a transaction identification using an incremental counter in the memory module;   generating a parity bit, using a parity generator in the memory module, from a combination of the transaction identification and the command and data address bits; and   synchronizing, via communication nodes of the memory module, the transaction identification between a memory controller of the memory module and the host.   
     
     
         7 . The non-transitory computer-readable medium of  claim 6 , wherein the operations include:
 comparing the generated transaction identification to a list of outstanding transaction identifications; and   comparing the generated parity bit to a running parity pattern.   
     
     
         8 . The non-transitory computer-readable medium of  claim 6 , wherein the operations include:
 calculating an error-correcting code for data, corresponding to a read command, from a combination including the data, an operational code, and a message; and   transmitting the data including the error-correcting code from the memory controller to the host.