Variable length instruction processor system and method

Abstract

A variable length instruction processor system and method is provided. Before a processor core executes an instruction, the system and method applied in a processor field convert the instruction into micro-operation(s)and the micro-operation(s) can be filled into a cache system that can be directly accessed by a processor core, reducing the depth of a pipeline and improving efficiency of the pipeline.

1 - 31 . (canceled) 
     
     
         32 . A method for processing first instructions of a first instruction set stored in a first memory using a processor core capable of processing second instructions of a second instruction set, comprising:
 converting a block of first instructions of a first instruction set to a block of second instructions of a second instruction set;   extracting and storing a mapping relationship between block offsets of the first instructions and the second instructions;   storing, in a second memory, a plurality of blocks of second instructions from the conversion;   indexing a second memory block using a block address;   indexing a second instruction from the indexed second memory block using a mapped block offset obtained by mapping of a block offset using the stored mapping relationship;   supplying the indexed second instruction to the processor core for processing;   providing the block address and the block offset under the control of the processor core.   
     
     
         33 . The method according to  claim 32 , further comprising:
 when processing a second instruction that does not change program flow, indexing a second instruction from the indexed block of second memory using the block offset without mapping.   
     
     
         34 . The method according to  claim 32 , further comprising:
 when processing a second instruction that changes program flow, providing a block address and a block offset as a branch target address;   when processing a second instruction which does not change program flow and is not a last instruction of a block, providing a block address as an unchanged previous block address and a block offset as a previous block offset increased by a length of a second instruction; or   when processing a second instruction that does not change program flow and is a last instruction of a block, providing a block address as the previous block address increased by a length of an instruction block, and a block offset of the first instruction of the block.   
     
     
         35 . The method according to  claim 32 , further comprising:
 identifying each direct branch instruction during conversion of the block of first instructions;   calculating a branch target instruction address for each direct branch instruction in the form of a block address and a block offset;   prefetching from a lower level memory a block of first instructions using the block address of each branch target address;   converting each block of first instructions containing the branch target instruction to the block of second instructions;   extracting and preserving the mapping relationship of branch offsets; and   storing in the second memory each block of second instructions.   
     
     
         36 . The method according to  claim 32 , further comprising:
 mapping a block address of a branch target instruction address into a second memory block number;   mapping a block offset of a branch target instruction address into a second memory block offset using the stored mapping relationship of block offsets;   storing the second memory block number and the second memory block offset into an entry of a track table which corresponds to a branch instruction;   when or before processing a branch instruction, reading out from an entry of a track table corresponding to the branch instruction;   addressing the second memory using the second memory block number and the second memory block offset in the read out entry of a track table;   providing the second instruction from the second memory to the processor core for processing.   
     
     
         37 . The method according to  claim 36 , further comprising:
 addressing the track table using a track address;   when the read out entry of track table is of a type which changes program flow and when a branch condition is meet, using the address in the entry of track table as the track address; otherwise, increasing the track address by the length of a second instruction.   
     
     
         38 . The method according to  claim 36 , further comprising:
 defining an end track point as an entry of a track table after the entry of a track table corresponding to a last second instruction in a second instruction block;   storing in the end track point a second memory block number and a second memory block offset of the first instruction of the next sequential second memory block in program order.   
     
     
         39 . The method according to  claim 38 , further comprising:
 setting the end track point to be a type which changes program flow and meeting branch condition;   when an end track point is read out from a track table, reading out from the track table next the entry specified by addresses in the end track point.   
     
     
         40 . The method according to  claim 37 , further comprising:
 controlling generation of a track address using a branch decision of the processor core;   addressing the track table using the track address;   addressing the second memory selecting a block of second instructions and addressing the block offset mapping relationship using the second memory block number read out from the track table;   when processing an second instruction which does not change program flow, selecting a second instruction from the selected block of second instructions using the processor core produced block offset; or   when processing an second instruction which changes program flow, selecting a second instruction from the selected block of second instructions using a mapped block offset obtained by mapping the processor core produced block offset using selected block offset mapping relationship.   
     
     
         41 . The method according to  claim 36 , further comprising:
 storing first instructions of a first instruction set in the first memory;   converting a block of first instructions from the first memory into a block of second instructions and storing the block of second instructions in the second memory;   calculating, mapping and storing in a track table the branch target instruction addresses during the conversion;   preserving the mapping relationship between block numbers in first memory and second memory; and   preserving the mapping relationship between block offsets of first instructions and second instructions.   
     
     
         42 . The method according to  claim 41 , further comprising:
 when a track table entry read out is of first memory address type, mapping the block number of first memory address into block number of second memory address using the stored mapping relationships of block number, mapping block offset the first memory address into block offset of second memory address using the stored mapping relationships of block offset; and replacing the first memory address in the track using the second memory address;   when a track table entry read out is of second memory address type, addressing the second memory using the second memory address to provide second instruction to the processor core.   
     
     
         43 . The method according to  claim 37 , further comprising:
 controlling generation of a track address using a branch decision of the processor core;   addressing a track table to read out a track table entry using the track address;   when a content of a track table entry is of a third memory address, addressing a third memory using the content of the track table entry to provide a block of first instructions, converting the block of first instructions to a block of second instructions and storing it in a block of a first memory, extracting and preserving in a third mapping memory the mapping relationship of third memory block number to first memory block number and mapping relationship of first instruction block offset to second instruction block offsets, and replacing the third memory address in the track table entry by a first memory address, which is first memory block number and second instruction block offset;   when a content of a track table entry is of a first memory address, addressing a first memory using the first memory block number in the track table entry to provide a block of second instructions, storing it in a block of a second memory, extracting and preserving in a second mapping memory the mapping relationship of first memory block number to second memory block number, and replacing the first memory address in the track table entry by a second address, which is a second memory block number and a second instruction block offset; or   addressing the second mapping memory to map a first memory block number to a second memory block number, replacing the first memory address in the track table entry by a second address;   when a content of the track table entry is of a second memory address, addressing a second memory using the second memory address in the track table entry to provide a second instruction to the processor core for processing.   
     
     
         44 . The method according to  claim 37 , further comprising:
 controlling generation of a track address using the branch decision of the processor core;   addressing a second track table to read out a second track table entry using the track address;   when a second track table entry is of a second memory address type, addressing a second memory using the content of the second track table entry to provide a second instruction to the processor core for processing;   when a second track table entry is of a first memory address type, addressing a first memory using the first memory address to read a block of second instructions, storing it to a block of second memory, and addressing a first track table using the first memory address to read a first track, to convert the first track to a second track and to store the second track to a second track table.   
     
     
         45 . The method according to  claim 44 , wherein converting the first track to a second track further comprises:
 converting a third memory address on a first track to be a first memory address on a second track while converting a block of first instructions in the third memory designated by the third memory address to a block of second instructions to be stored in the first memory, while extracting and preserving the mapping relationship of third memory block number to first memory block number and the mapping relationship of first instruction block offset to second instruction block offset; and   converting a first memory address on a first track to be a second memory address on a second track while reading a block of second instructions in the first memory designated by the first memory address to a block of second instructions to be stored in the second memory, while preserving the mapping relationship of first memory block number to second memory block number.   
     
     
         46 . The method according to  claim 32 , further comprising:
 addressing the second memory using a block address to read out a block of second instructions;   storing in an instruction read buffer (IRB) the block of second instructions together with corresponding block number and block offset;   inserting a token in the IRB at a position of a second instruction with matching block number and block offset;   passing the token following order of instructions in the block of second instructions in the IRB;   issuing from IRB to the processor core the second instruction corresponding to the position of the token.   
     
     
         47 . The method according to  claim 37 , further comprising:
 controlling generation of a track address using a branch decision of the processor core;   addressing the track table using the track address to read out an entry of track table;   addressing the second memory to read out a block of second instructions from the second memory using the second memory block number from the entry of the track table;   storing the block of second instructions to the IRB;   addressing the IRB using the block number and block offset of second memory read out from the track table;   serving second instructions to the processor core by the IRB; and   pointing the track address to a next track table entry which corresponds to a branch instruction.   
     
     
         48 . The method according to  claim 32 , further comprising:
 storing a block offset mapping relationship between a block of first instructions and a block of second instructions as one row of entries, where each entry corresponding to a block offset of a beginning of a first instruction stores a block offset of a beginning of a corresponding second instruction.   
     
     
         49 . The method according to  claim 32 , further comprising:
 storing a block offset mapping relationship between a block of first instructions and a block of second instructions as pairs of block offsets, where each block offset of a beginning of a first instruction pairs with a block offset of a beginning of a corresponding second instruction.   
     
     
         50 . The method according to  claim 32 , further comprising:
 recording in relate to each instruction block the length of a portion of a last instruction that situates in a next instruction block; and   converting the next instruction block starting at a block offset immediate after the recorded length.   
     
     
         51 . The method according to  claim 32 , further comprising:
 storing a block offset mapping relationship between a block of first instructions and a block of second instructions as two rows of states, the first row representing block offset of the first instructions while the second row representing block offset of the second instructions, where a state represents a beginning of an instruction while another state represents other parts of an instruction;   aligning to LSB position when storing second instructions and block offset mapping relationship resulting from the first conversion of a first instruction block;   aligning to MSB position in reverse order when storing the second instructions and block offset mapping relationship resulting from the second conversion of a first instruction block; and   aligning to the last stored position in reverse order when storing the second instructions and block offset mapping relationship resulting from further conversion of a first instruction block;   recording the last stored position as a starting position;   rotating the block offset mapping relationship to align the starting position to the LSB position before using the block offset mapping relationship to map a block offset of a first instruction to a block offset of a second instruction;   adjusting the block offset of a second instruction by the rotation amount to address the corresponding block of second instructions.