Methods for optimizing circuit performance via configurable clock skews

Abstract

An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a first stage of combinational logic circuitry in programmable logic fabric of the integrated circuit device, wherein the first stage of combinational logic circuitry is disposed between a first latch and a second latch; and   a second stage of combinational logic circuitry in programmable logic fabric of the integrated circuit device, wherein the second stage of combinational logic circuitry is disposed between the second latch and a third latch;   wherein:
 the first stage of combinational logic circuitry has a first delay and wherein the second stage of combinational logic circuitry has a second delay that is different from the first delay by a first time difference; 
 the first latch is clocked to a first clock, the second latch is clocked to a second clock, and the third latch is clocked to the first clock, wherein the first clock and the second clock have the same frequency, and wherein at least one clock edge of the first clock is out of phase with at least one clock edge of the second clock by a second time difference; and 
 the second time difference between the at least one clock edge of the first clock and the at least one clock edge of the second clock accommodates at least part of the first time difference between the first delay and the second delay between the first stage of combinational logic circuitry and the second stage of combinational logic circuitry. 
   
     
     
         2 . An article of manufacture comprising one or more tangible, non-transitory, machine-readable instructions that, when executed, cause one or more processors to:
 receive a circuit design specification; and   perform placement or routing of circuit elements from the circuit design specification, wherein the placement or routing of circuit elements enables time borrowing between a first stage of circuit elements that has a first delay and a second stage of circuit elements that has a second delay different from the first at least in part by:
 providing a first latch; 
 providing a first clock signal to control the first latch, wherein the first clock signal has a first frequency; 
 providing the first stage immediately after the first latch; 
 providing a second latch immediately after the first stage; 
 providing a second clock signal to control the second latch, wherein the second clock signal has the first frequency and comprises at least one clock edge that that has an offset from a corresponding clock edge of the first clock signal; and 
 providing the second stage immediately after the second latch; 
   wherein the offset enables time borrowing of the first stage from the second stage or of the second stage from the first stage.   
     
     
         3 . A data processing system comprising:
 a system processor; and   a programmable logic device communicatively coupled to the processor, wherein the programmable logic device comprises:
 a first stage of combinational logic circuitry in programmable logic fabric of the programmable logic device, wherein the first stage of combinational logic circuitry is disposed between a first latch and a second latch; and 
 a second stage of combinational logic circuitry in programmable logic fabric of the programmable logic device, wherein the second stage of combinational logic circuitry is disposed between the second latch and a third latch; 
 wherein:
 the first stage of combinational logic circuitry has a first delay and wherein the second stage of combinational logic circuitry has a second delay that is different from the first delay by a first time difference; 
 the first latch is clocked to a first clock, the second latch is clocked to a second clock, and the third latch is clocked to the first clock, wherein the first clock and the second clock have the same frequency, and wherein at least one clock edge of the first clock is out of phase with at least one clock edge of the second clock by a second time difference; and 
 the second time difference between the at least one clock edge of the first clock and the at least one clock edge of the second clock accommodates at least part of the first time difference between the first delay and the second delay between the first stage of combinational logic circuitry and the second stage of combinational logic circuitry.