Integrated circuit package comprising surface capacitor and ground plane

Abstract

Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

What is claimed is: 
     
         1 . A method for manufacturing an integrated circuit package comprising:
 providing a substrate having a plurality of build-up layers;   providing a vertical capacitor;   attaching a first electrode of the vertical capacitor to a first substrate pad embedded in a first layer of the plurality of build-up layers of the substrate;   forming a conductive layer on a portion of the first layer of the plurality of build-up layers of the substrate and on a second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor; and   attaching an integrated circuit die to a first plurality of substrate pads embedded in the first layer of the substrate.   
     
     
         2 . The method of  claim 1 , wherein the first and second electrodes of the vertical capacitor are perpendicularly located to a planar surface of the substrate. 
     
     
         3 . The method of  claim 1 , wherein the substrate has a thickness range of 160-190 microns. 
     
     
         4 . The method of  claim 1 , wherein the substrate has a thickness of 176 microns. 
     
     
         5 . The method of  claim 1 , wherein the vertical capacitor has a width of 0.5 millimeter and a thickness range of 0.1-0.2 millimeter. 
     
     
         6 . The method of  claim 1 , wherein the substrate comprises:
 a first and a second prepreg layers;   a first redistribution layer located on the first prepreg layer, wherein each substrate pad embedded in the first layer of the substrate is formed on the first redistribution layer, wherein the first layer of the substrate is a solder resist layer;   a metal layer located between the first and second prepreg layers;   a second redistribution layer located on a surface of the second prepreg layer; and   a second dielectric layer located on the second redistribution layer.   
     
     
         7 . The method of  claim 6 , wherein each of the first and second prepreg layers has a thickness of 45 microns. 
     
     
         8 . The method of  claim 6 , wherein each of the first and second prepreg layers has a different coefficient of thermal expansion (CTE). 
     
     
         9 . The method of  claim 1 , wherein forming the conductive layer comprises coupling the conductive layer to at least one substrate pad embedded in the first layer of the substrate. 
     
     
         10 . The method of  claim 9 , wherein forming the conductive layer comprises spraying the conductive layer on the first layer of the substrate after attaching the first electrode of the capacitor to the substrate. 
     
     
         11 . The method of  claim 9 , wherein forming the conductive layer comprises electroplating the conductive layer on the first layer of the substrate after attaching the first electrode of the capacitor to the substrate. 
     
     
         12 . The method of  claim 9 , wherein forming the conductive layer comprises coupling the conductive layer to a second and third substrate pads, wherein the second substrate pad is electrically coupled to the integrated circuit die via a conductive trace in a first redistribution layer of the plurality of build-up layers. 
     
     
         13 . The method of  claim 12 , wherein the second substrate pad is coupled to a ground or a power plane. 
     
     
         14 . An integrated circuit package comprising:
 a substrate comprising a first plurality of substrate pads;   an integrated circuit die coupled to the first plurality of substrate pads embedded in a first layer of the substrate;   a vertical capacitor having a first electrode, a second electrode and a first resistive layer, the first electrode coupled to the first resistive layer, the first resistive layer coupled to a first substrate pad embedded in the first layer of the substrate; and   a conductive layer formed over a first surface and the second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor, and wherein the first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.   
     
     
         15 . The integrated circuit package of  claim 14 , wherein the vertical capacitor further includes a second resistive layer coupled to the second electrode, wherein the conductive layer is formed over the second resistive layer. 
     
     
         16 . An integrated circuit package comprising:
 a coreless substrate having a plurality of build-up layers;   an integrated circuit die coupled to a first plurality of substrate pads embedded in a first layer of the plurality of build-up layers of the substrate;   a vertical capacitor having first and second electrodes with a common axis being perpendicular to a planar surface of the substrate, the vertical capacitor further having a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer are formed over part of the first electrode, the first electrode is coupled to a first substrate pad embedded in the first layer of the substrate; and   a conductive layer formed over the first insulating layer, the second insulating layer and the second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor, wherein the plurality of build-up layers comprise two prepreg layers, and wherein each prepreg layer has a thickness range of 30-60 microns.   
     
     
         17 . The integrated circuit package of  claim 16 , wherein the vertical capacitor further includes a first resistive layer coupled to the first electrode, wherein the first resistive layer is between the first electrode and the first substrate pad. 
     
     
         18 . The integrated circuit package of  claim 17 , wherein the first insulating layer and the second insulating layer are formed over part of the first resistive layer. 
     
     
         19 . The integrated circuit package of  claim 17 , wherein the vertical capacitor further includes a second resistive layer coupled to the second electrode, wherein the conductive layer is formed over the second resistive layer. 
     
     
         20 . The integrated circuit package of  claim 19 , wherein the vertical capacitor comprises a plurality of interleaved vertical metal layers, each interleaved vertical metal layer consisting of a single metal layer.