US2019051583A1PendingUtilityA1

Semiconductor device and method for manufacturing the same

Assignee: RENESAS ELECTRONICS CORPPriority: Jan 22, 2015Filed: Oct 16, 2018Published: Feb 14, 2019
Est. expiryJan 22, 2035(~8.5 yrs left)· nominal 20-yr term from priority
H10W 90/756H10W 90/754H10W 90/736H10W 90/734H10W 74/10H10W 74/00H10W 72/5525H10W 72/5524H10W 72/5522H10W 72/5473H10W 72/5445H10W 72/5366H10W 72/932H10W 72/884H10W 72/352H10W 72/0198H10W 72/075H10W 72/073H10W 72/59H10W 46/503H10W 74/111H10W 74/016H10W 72/90H10W 46/00H10W 70/421H01L 2224/45144H01L 23/3107H01L 23/49541H01L 2224/04042H01L 23/544H01L 2224/45124H01L 2224/45147H01L 2924/3862H01L 2223/5446H01L 21/565H01L 2224/94H01L 24/49H01L 2224/48247H10W 72/851H10W 72/50H10W 72/30
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Claims

Abstract

A semiconductor device PKG includes a semiconductor chip CP, a lead LD 3, a wire BW 5 electrically connecting a pad electrode PD 2 of the semiconductor chip CP to the lead LD 3, a wire BW 3 electrically connecting a pad electrode PD 3 of the semiconductor chip CP to the lead LD 3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5 b and 5 c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5 c and the pad electrode PD 3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5 b and the pad electrode PD 2, and in a second state in which signal transmission is not possible between the internal circuit 5 b and the pad electrode PD 2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a semiconductor chip having a main surface on which a first pad and a second pad are formed;   a first electrode disposed around the semiconductor chip;   a first wire electrically connecting the first pad to the first electrode;   a second wire electrically connecting the second pad to the first electrode; and   a sealing body sealing the semiconductor chip, the first wire, and the second wire with a resin,
 wherein a signal is transmitted between the first electrode and the semiconductor chip via the second electrode and the second wire, and a signal is not transmitted between the first electrode and the semiconductor chip via the first electrode and the first wire. 
   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a third pad formed in the main surface of the semiconductor chip;
 a second electrode disposed around the semiconductor chip; 
 a third wire electrically connecting the third pad to the second electrode, 
 wherein a signal is transmitted between the semiconductor chip and the second electrode via the third pad and the third wire, 
 wherein, in a plan view, the first pad, the second pad, and the third pad are disposed along a first side of the main surface of the semiconductor chip, and 
 wherein the first pad is disposed between the second pad and the third pad. 
   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising:
 a fourth pad formed in the main surface of the semiconductor chip;   a third electrode disposed around the semiconductor chip; and   a fourth wire electrically connecting the fourth pad to the third electrode,   wherein a signal is transmitted between the semiconductor chip and the third electrode via the fourth pad and the fourth wire,   wherein, in the plan view, the fourth pad is disposed along the first side of the main surface of the semiconductor chip, and   wherein the second pad is disposed between the fourth pad and the first pad.   
     
     
         4 . The semiconductor device according to  claim 3 , further comprising:
 a plurality of fifth pads formed on the main surface of the semiconductor chip,   wherein, in the plan view, the plurality of fifth pads are disposed along the first side of the main surface of the semiconductor chip, and   wherein the plurality of fifth pads are disposed between the first pad and the second pad and between the first pad and the third pad.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the each of the fifth pads is not connected with a wire.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein a pad is not disposed between the second pad and the fourth pad in the plan view.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein a part of the first electrode is exposed from the sealing body.   
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 a wiring substrate on which the semiconductor chip is mounted, and   wherein the first electrode is formed on the wiring substrate.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the sealing body has a resin injection mark, and   wherein the first wire is located at a closer position to the resin injection mark than the second wire.   
     
     
         10 . A semiconductor device comprising:
 a semiconductor chip having a main surface on which a first pad and a second pad are formed;   a first electrode disposed around the semiconductor chip;   a first wire electrically connecting the first pad to the first electrode;   a second wire electrically connecting the second pad to the first electrode; and   a sealing body sealing the semiconductor chip, the first wire, and
 the second wire with a resin.

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