Digital-to-analog converter (dac) with enhanced dynamic element matching (dem) and calibration

Abstract

In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.

What is claimed is: 
     
         1 . A system comprising:
 a digital-to-analog converter (DAC) that is configured to apply digital-to-analog conversions, the DAC comprising:
 one or more conversion circuits, wherein each conversion circuit is configured to handle one or more bits in an input to the DAC; and 
 one or more control circuits configured to apply:
 detect one or more types of errors that occur during operation of the DAC; 
 determine one or more adjustments for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors; 
 apply at least one of the one or more adjustments, wherein the one or more control circuits are configured to apply at least one of the one or more adjustments to only a subset of the one or more conversion circuits. 
 
   
     
     
         2 . The system of  claim 1 , wherein the DAC is configured to switch among a plurality of modes; and
 the one or more control circuits are configured to apply adjustments only in one or more of the plurality of modes but not in all of the plurality of modes.   
     
     
         3 . The system of  claim 2 , wherein the plurality of modes comprises a normal mode and a correction mode; and
 the one or more control circuits are configured to apply adjustments only during the correction mode.   
     
     
         4 . The system of  claim 1 , wherein the one or more control circuits are configured to apply adjustments during active operation of the DAC. 
     
     
         5 . The system of  claim 1 , wherein:
 the DAC comprises a plurality of segments, with each segment comprising one or more of the conversion circuits; and   the one or more control circuits are configured to apply adjustments to only one or more of the plurality of segments.   
     
     
         6 . The system of  claim 5 , comprising a selector circuit configured for facilitating applying adjustments to one of the plurality of segments. 
     
     
         7 . The system of  claim 5 , wherein the plurality of segments comprises:
 a most significant bits (LSBs) segment;   an upper LSBs (ULSBs) segment; and   a least significant bits (LSBs) segment.   
     
     
         8 . The system of  claim 7 , wherein the one or more control circuits are configured to apply adjustments to only to the ULSBs segment. 
     
     
         9 . The system of  claim 1 , wherein the one or more types of errors comprise mismatch errors, and the one or more effects resulting from errors comprise spurs. 
     
     
         10 . A method comprising:
 applying digital-to-analog conversion via a digital-to-analog converter (DAC) to an input signal, wherein the DAC comprises one or more conversion circuits, with each conversion circuit configured to handle one or more bits in the input signal;   detecting one or more types of errors that occur during operation of the DAC;   determining one or more adjustments for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors;   applying at least one of the one or more adjustments, wherein the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits.   
     
     
         11 . The method of  claim 10 , comprising adaptively switching the DAC among a plurality of modes; and
 the one or more control circuits are configured to apply adjustments only in one or more of the plurality of modes but not in all of the plurality of modes.   
     
     
         12 . The method of  claim 11 , wherein the plurality of modes comprises a normal mode and a correction mode. 
     
     
         13 . The method of  claim 12 , comprising applying adjustments only during the correction mode. 
     
     
         14 . The method of  claim 10 , comprising applying adjustments during active operation of the DAC. 
     
     
         15 . The method of  claim 10 , wherein the DAC comprises a plurality of segments, with each segment comprising one or more of the conversion circuits; and comprising applying adjustments to only one or more of the plurality of segments. 
     
     
         16 . The method of  claim 15 , wherein the plurality of segments comprises:
 a most significant bits (LSBs) segment;   an upper LSBs (ULSBs) segment; and   a least significant bits (LSBs) segment; and   comprising applying adjustments to only to the ULSBs segment.   
     
     
         17 . The method of  claim 10 , wherein the one or more types of errors comprise mismatch errors, and the one or more effects resulting from errors comprise spurs.