Storage device having programmed cell storage density modes that are a function of storage device capacity utilization

Abstract

A method is described. The method includes programming multi-bit storage cells of multiple FLASH memory chips in a lower density storage mode. The method also includes programming the multi-bit storage cells of the multiple FLASH memory chips in a higher density storage mode after at least 25% of the storage capacity of the multiple FLASH memory chips has been programmed.

What is claimed: 
     
         1 . An apparatus, comprising:
 a storage device comprising a controller and a plurality of FLASH memory chips, the plurality of FLASH memory chips comprising three-dimensional stacks of multi-bit storage cells, the multi-bit storage cells having multiple storage density modes, the controller to program the cells in a lower density storage mode up to a storage capacity threshold of the storage device of at least 25%, the controller to program the cells in a higher density mode once the capacity threshold is reached.   
     
     
         2 . The apparatus of  claim 1  wherein the lower density storage mode is multi-level cell (MLC). 
     
     
         3 . The apparatus of  claim 2  wherein the higher density storage mode is quad level cell (QLC). 
     
     
         4 . The apparatus of  claim 3  wherein the storage capacity threshold is 50%. 
     
     
         5 . The apparatus of  claim 1  wherein the storage capacity threshold is within a range of 25% to 75% inclusive. 
     
     
         6 . The apparatus of  claim 1  wherein the higher density storage mode is QLC. 
     
     
         7 . The apparatus of  claim 1  wherein the storage device is a solid state drive. 
     
     
         8 . An apparatus, comprising:
 a controller to determine programming levels for a plurality of FLASH memory chips, the plurality of FLASH memory chips comprising three-dimensional stacks of multi-bit storage cells, the multi-bit storage cells having multiple storage density modes, the controller to program the cells in a lower density storage mode up to a storage capacity threshold of the FLASH memory chips of at least 25%, the controller to program the cells in a higher density storage mode once the capacity threshold is reached.   
     
     
         9 . The apparatus of  claim 8  wherein the lower density storage mode is multi-level cell (MLC). 
     
     
         10 . The apparatus of  claim 9  wherein the higher density storage mode is quad level cell (QLC). 
     
     
         11 . The apparatus of  claim 10  wherein the storage capacity threshold is 50%. 
     
     
         12 . The apparatus of  claim 8  wherein the storage capacity threshold is within a range of 25% to 75% inclusive. 
     
     
         13 . The apparatus of  claim 8  wherein the higher density storage mode is QLC. 
     
     
         14 . The apparatus of  claim 8  wherein the controller and plurality of FLASH memory chips are components of a solid state drive. 
     
     
         15 . A computing system, comprising:
 a plurality of processing cores;   a main memory;   a memory controller coupled between the plurality of processing cores and the main memory;   a peripheral hub controller; and,   a solid state drive coupled to the peripheral hub controller, the solid state drive comprising a controller and a plurality of FLASH memory chips, the plurality of FLASH memory chips comprising three-dimensional stacks of multi-bit storage cells, the multi-bit storage cells having multiple storage density modes, the controller to program the cells in a lower density storage mode up to a storage capacity threshold of the storage device of at least 25%, the controller to program the cells in a higher density storage mode once the capacity threshold is reached.   
     
     
         16 . The computing system of  claim 15  wherein the lower density storage mode is multi-level cell (MLC). 
     
     
         17 . The computing system of  claim 16  wherein the higher density storage mode is quad level cell (QLC). 
     
     
         18 . The computing system of  claim 17  wherein the storage capacity threshold is 50%. 
     
     
         19 . The computing system of  claim 15  wherein the storage capacity threshold is within a range of 25% to 75% inclusive. 
     
     
         20 . An article of manufacture comprising stored program code that when processed by a controller of a storage device having multiple FLASH memory chips causes the storage device to perform a method, comprising:
 programming multi-bit storage cells of the multiple FLASH memory chips in a lower density storage mode; and,   programming the multi-bit storage cells of the multiple FLASH memory chips in a higher density storage mode after at least 25% of the storage capacity of the multiple FLASH memory chips has been programmed.